AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 105

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
Watchdog Timer Control Register – WDTCR
• Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the FPSLIC and will always read as zero.
• Bit 4 - WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be
disabled. Once set, the hardware will clear this bit to zero after four clock cycles. Refer to the
description of the WDE bit below for a watchdog disable procedure.
• Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, but if the WDE is cleared (zero),
the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set
(one). To disable an enabled Watchdog Timer, the following procedure must be followed:
• Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding Time-out
periods are shown in Table 32.
Table 32. Watchdog Timer Prescale Select
Note:
Bit
$21 ($41)
Read/Write
Initial Value
WDP2
1. In the same operation, write a logic 1 to WDTOE and WDE. A logic 1 must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
0
0
0
0
1
1
1
1
ten to WDE even though it is set to one before the disable operation starts.
watchdog.
1. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical
Characteristics section. The WDR (watchdog reset) instruction should always be executed
before the Watchdog Timer is enabled. This ensures that the reset period will be in accor-
dance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the Watchdog Timer may not start counting from zero.
7
-
R
0
WDP1
0
0
1
1
0
0
1
1
6
-
R
0
WDP0
0
1
0
1
0
1
0
1
5
-
R
0
4
WDTOE
R/W
0
Oscillator Cycles
Number of WDT
1,024K
2,048K
128K
256K
512K
16K
32K
64K
3
WDE
R/W
0
AT94K Series FPSLIC
(1)
2
WDP2
R/W
0
1
WDP1
R/W
0
Typical Time-out
at V
47 ms
94 ms
0
WDP0
R/W
0
0.19s
0.38s
0.75s
CC
1.5s
3.0s
6.0s
= 3.0V
WDTCR
105