AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 11

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
most RAM blocks, RAddr is on the left and WAddr is on the right. For the right-most RAM
blocks, WAddr is on the left and RAddr is tied off. For single-ported RAM, WAddr is the
READ/WRITE address port and Din is the (bi-directional) data port. The right-most RAM
blocks can be used only for single-ported memories. WE and OE connect to the vertical
express buses in the same column on Plane V
OE connect to express buses that are full length at array edge.
Reading and writing the 32 x 4 dual-port RAM are independent of each other. Reading the 32
x 4 dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1,
data flows through; when Load is logic 0, data is latched. Each bit in the 32 x 4 dual-port RAM
is also a transparent latch. The front-end latch and the memory latch together and form an
edge-triggered flip-flop. When a bit nibble is (Write) addressed and LOAD is logic 1 and WE is
logic 0, DATA flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0
or WE is logic 1, DATA is latched in the nibble. The two CLOCK muxes are controlled
together; they both select CLOCK or they both select “1”. CLOCK is obtained from the clock
for the sector-column immediately to the left and immediately above the RAM block. Writing
any value to the RAM Clear Byte during configuration clears the RAM, see Figure 5 and
Figure 6.
Figure 8. FPGA RAM Connections (One RAM Block)
1
and V
AT94K Series FPSLIC
2
, respectively. WAddr, RAddr, WE and
CLK
CLK
CLK
CLK
CLK
WAddr
WE
OE
32X4 RAM
Din
Sector Clock Mux
Dout
RAddr
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