AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 113

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Example 5 –
Basic Usage
8-bit x 8-bit = 16-bit
Signed Fractional
Multiply
Example 6 – Multiply-
accumulate Operation
Rev. 1138F–FPSLI–06/02
To convert a negative fractional number, first add 2 to the number and then use the same
algorithm as already shown.
16-bit fractional numbers use a format similar to that of 8-bit fractional numbers; the high 8 bits
have the same format as the 8-bit format. The low 8 bits are only an increase of accuracy of
the 8-bit format; while the 8-bit format has an accuracy of ± 2
racy of ± 2
16-bit fractional numbers. Note the important difference between integers and fractional num-
bers when extra byte(s) are used to store the number: while the accuracy of the numbers is
increased when fractional numbers are used, the range of numbers that may be represented
is extended when integers are used.
As mentioned earlier, using signed fractional numbers in the range [-1, 1> has one main
advantage to integers: when multiplying two numbers in the range [-1, 1>, the result will be in
the range [-1, 1], and an approximation (the highest byte(s)) of the result may be stored in the
same number of bytes as the factors, with one exception: when both factors are -1, the prod-
uct should be 1, but since the number 1 cannot be represented using this number format, the
FMULS instruction will instead place the number -1 in R1:R0. The user should therefore
assure that at least one of the operands is not -1 when using the FMULS instruction. The
16-bit x 16-bit fractional multiply also has this restriction.
This example shows an assembly code that reads the port E input value and multiplies this
value with a fractional constant (-0.625) before storing the result in register pair R17:R16.
Note that the usage of the FMULS (and FMUL) instructions is very similar to the usage of the
MULS and MUL instructions.
The example below uses data from the ADC. The ADC should be configured so that the for-
mat of the ADC result is compatible with the fractional two’s complement format. For the
ATmega83/163, this means that the ADLAR bit in the ADMUX I/O register is set and a differ-
ential channel is used. The ADC result is normalized to one.
The registers R19:R18:R17:R16 will be incremented with the result of the multiplication of
0.771484375 with the ADC conversion result. In this example, the ADC result is treated as a
signed fraction number. We could also treat it as a signed integer and call it “mac16x16_32”
instead of “fmac16x16_32”. In this case, the 0.771484375 should be replaced with an integer.
in
ldi
fmuls r16,r17
movw r17:r16,r1:r0; Move the result to the r17:r16
ldi r23,$62
ldi r22,$C0
in
in
callfmac16x16_32
r20,ADCL
r21,ADCH
r16,PINE
r17,$B0
-16
. Then again, the 32-bit fractional numbers are an increase of accuracy to the
; Read pin values
; Load -0.625 into r17
; r1:r0 = r17 * r16
; register pair
; Load highbyte of
; fraction 0.771484375
; Load lowbyte of
; fraction 0.771484375
; Get lowbyte of ADC conversion
; Get highbyte of ADC conversion
;Call routine for signed fractional
; multiply accumulate
AT94K Series FPSLIC
-8
, the16-bit format has an accu-
113