AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 120

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

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AT94K Series FPSLIC
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Reg-
ister, UDRn. Data is transferred from UDRn to the Transmit shift register when:
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If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDRn to the shift
register. At this time the UDREn (UART Data Register Empty) bit in the UART Control and
Status Register, UCSRnA, is set. When this bit is set (one), the UART is ready to receive the
next character. At the same time as the data is transferred from UDRn to the 10(11)-bit shift
register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If a 9-bit
data word is selected (the CHR9n bit in the UART Control and Status Register, UCSRnB is
set), the TXB8 bit in UCSRnB is transferred to bit 9 in the Transmit shift register.
On the Baud-rate clock following the transfer operation to the shift register, the start bit is
shifted out on the TXDn pin. Then follows the data, LSB first. When the stop bit has been
shifted out, the shift register is loaded if any new data has been written to the UDRn during the
transmission. During loading, UDREn is set. If there is no new data in the UDRn register to
send when the stop bit is shifted out, the UDREn flag will remain set until UDRn is written
again. When no new data has been written, and the stop bit has been present on TXDn for
one bit length, the TX Complete flag, TXCn, in UCSRnA is set.
The TXENn bit in UCSRnB enables the UART transmitter when set (one). When this bit is
cleared (zero), the PE0 (UART0) or PE2 (UART1) pin can be used for general I/O. When
TXENn is set, the UART Transmitter will be connected to PE0 (UART0) or PE2 (UART1),
which is forced to be an output pin regardless of the setting of the DDE0 bit in DDRE (UART0)
or DDE2 in DDRE (UART1).
A new character has been written to UDRn after the stop bit from the previous character
has been shifted out. The shift register is loaded immediately.
A new character has been written to UDRn before the stop bit from the previous character
has been shifted out. The shift register is loaded when the stop bit of the character
currently being transmitted has been shifted out.
Rev. 1138F–FPSLI–06/02