AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 125

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
• Bit 3 - OR0/OR1: OverRun
This bit is set if an Overrun condition is detected, i.e., when a character already present in the
UDRn register is not read before the next character has been shifted into the Receiver Shift
register. The ORn bit is buffered, which means that it will be set once the valid data still in
UDRn is read.
The ORn bit is cleared (zero) when data is received and transferred to UDRn.
• Bit 2 - Res: Reserved Bit
This bit is reserved in the AT94K and will always read as zero.
• Bits 1 - U2X0/U2X1: Double the UART Transmission Speed
When this bit is set (one) the UART speed will be doubled. This means that a bit will be trans-
mitted/received in eight CPU clock periods instead of 16 CPU clock periods. For a detailed
description, see “Double Speed Transmission” on page 128”.
• Bit 0 - MPCM0/MPCM1: Multi-processor Communication Mode
This bit is used to enter Multi-processor Communication Mode. The bit is set when the Slave
MCU waits for an address byte to be received. When the MCU has been addressed, the MCU
switches off the MPCMn bit, and starts data reception.
For a detailed description, see “Multi-processor Communication Mode” on page 123.
UART0 Control and Status Registers – UCSR0B
UART1 Control and Status Registers – UCSR1B
• Bit 7 - RXCIE0/RXCIE1: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXCn bit in UCSRnA will cause the Receive Com-
plete interrupt routine to be executed provided that global interrupts are enabled.
• Bit 6 - TXCIE0/TXCIE1: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXCn bit in UCSRnA will cause the Transmit Com-
plete interrupt routine to be executed provided that global interrupts are enabled.
• Bit 5 - UDRIE0/UDREI1: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDREn bit in UCSRnA will cause the UART Data
Register Empty interrupt routine to be executed provided that global interrupts are enabled.
• Bit 4 - RXEN0/RXEN1: Receiver Enable
This bit enables the UART receiver when set (one). When the receiver is disabled, the TXCn,
ORn and FEn status flags cannot become set. If these flags are set, turning off RXENn does
not cause them to be cleared.
Bit
$0A ($2A)
Read/Write
Initial Value
Bit
$01 ($21)
Read/Write
Initial Value
7
RXCIE0
R/W
0
7
RXCIE1
R/W
0
6
TXCIE0
R/W
0
6
TXCIE1
R/W
0
5
UDRIE0
R/W
0
5
UDRIE1
R/W
0
4
RXEN0
R/W
0
4
RXEN1
R/W
0
3
TXEN0
R/W
0
3
TXEN1
R/W
0
AT94K Series FPSLIC
2
CHR90
R/W
0
2
CHR91
R/W
0
1
RXB80
R
1
1
RXB81
R
1
0
TXB80
R/W
0
0
TXB81
R/W
0
UCSR0B
UCSR1B
125