AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 128

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Double Speed
Transmission
The Baud-rate
Generator in Double
UART Speed Mode
128
AT94K Series FPSLIC
UART0 Baud-rate Register Low Byte – UBRR0
UART1 Baud-rate Register Low Byte – UBRR1
UBRRn stores the 8 least significant bits of the UART baud-rate register.
The FPSLIC provides a separate UART mode that allows the user to double the communica-
tion speed. By setting the U2X bit in UART Control and Status Register UCSRnA, the UART
speed will be doubled. The data reception will differ slightly from normal mode. Since the
speed is doubled, the receiver front-end logic samples the signals on the RXDn pin at a fre-
quency 8 times the baud-rate. While the line is idle, one single sample of logic 0 will be
interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let
sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples
the RXDn pin at samples 4, 5 and 6. If two or more of these three samples are found to be
logic 1s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-
to-0 transition.
If however, a valid start bit is detected, sampling of the data bits following the start bit is per-
formed. These bits are also sampled at samples 4, 5 and 6. The logical value found in at least
two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift
register as they are sampled. Sampling of an incoming character is shown in Figure 67.
Figure 67. Sampling Received Data when the Transmission Speed is Doubled
Note that the baud-rate equation is different from the equation
speed is doubled:
•
•
•
Note:
For standard crystal frequencies, the most commonly used baud-rates can be generated by
using the UBR settings in Table 35. UBR values which yield an actual baud-rate differing less
than 1.5% from the target baud-rate, are bold in the table. However since the number of sam-
ples are reduced and the system clock might have some variance (this applies especially
when using resonators), it is recommended that the baud-rate error is less than 0.5%. See
Table 36 for the UBR settings at various crystal frequencies in double UART speed mode.
Bit
$09 ($29)
Read/Write
Initial Value
Bit
$00 ($20)
Read/Write
Initial Value
SAMPLING
RECEIVER
BAUD = Baud-rate
f
UBR = Contents of the UBRRHI and UBRRn Registers, (0 - 4095)
CK
RXD
= Crystal Clock Frequency
1. This equation is only valid when the UART transmission speed is doubled.
START BIT
7
MSB
R/W
0
7
MSB
R/W
0
D0
6
R/W
0
6
R/W
0
D1
5
R/W
0
5
R/W
0
BAUD
D2
4
R/W
0
4
R/W
0
=
----------------------------- -
8(UBR
D3
f
CK
3
R/W
0
3
R/W
0
+
D4
1 )
2
R/W
0
2
R/W
0
D5
(1)
at page 126 when the UART
1
R/W
0
1
R/W
0
D6
Rev. 1138F–FPSLI–06/02
0
LSB
R/W
0
0
LSB
R/W
0
D7
STOP BIT
UBRR0
UBRR1