AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 150

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AT94K05AL

Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet

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LowPortE as General
Digital I/O
Alternate Functions
of PortE
150
AT94K Series FPSLIC
PEn, General I/O pin: The DDEn bit in the DDRE register selects the direction of this pin. If
DDEn is set (one), PEn is configured as an output pin. If DDEn is cleared (zero), PEn is config-
ured as an input pin. If PEn is set (one) when configured as an input pin, the MOS pull-up
resistor is activated. To switch the pull-up resistor off the PEn has to be cleared (zero) or the
pin has to be configured as an output pin. The port pins are input with pull-up when a reset
condition becomes active, even if the clock is not running.
Table 47. DDEn
Note:
• PortE, Bit 0
UART0 Transmit Pin.
• PortE, Bit 1
UART0 Receive Pin. Receive Data (Data input pin for the UART0). When the UART0 receiver
is enabled this pin is configured as an input regardless of the value of DDRE0. When the
UART0 forces this pin to be an input, a logic 1 in PORTE0 will turn on the internal pull-up.
• PortE, Bit 2
UART1 Transmit Pin. The alternate functions of Port E as UART0 pins are enabled by setting
bit SCR52 in the FPSLIC System Control Register. This is necessary only in smaller pinout
packages where the UART signals are not bonded out. The alternate functions of Port E as
UART1 pins are enabled by setting bit SCR53 in the FPSLIC System Control Register.
• PortE, Bit 3
UART1 Receive Pin. Receive Data (Data input pin for the UART1). When the UART1 receiver
is enabled this pin is configured as an input regardless of the value of DDRE2. When the
UART1 forces this pin to be an input, a logic 1 in PORTE2 will turn on the internal pull-up.
• PortE, Bit 4-7
External Interrupt sources 0/1/2/3: The PE4 – PE7 pins can serve as external interrupt
sources to the MCU. Interrupts can be triggered by low-level on these pins. The internal pull-
up MOS resistors can be activated as described above.
The alternate functions of PortE as Interrupt pins by setting a bit in the System Control Regis-
ter. INT0 is controlled by SCR48. INT1 is controlled by SCR49. INT2 is controlled by SCR50.
INT3 is controlled by SCR51.
PortE, Bit 7 also shares a pin with the configuration control signal CHECK. Lowering CON to
initiate an FPSLIC download (whether for loading or Checking) causes the PE7/CHECK pin to
immediately tri-state. This function happens only if the Check pin has been enabled in the sys-
tem control register. The use of the Check pin will NOT disable the use of that pin as an input
to PE7 nor as an input as alternate INT3.
DDEn
0
0
1
1
(1)
1. n: 7,6...0, pin number
PORTEn
(1)
0
1
0
1
Bits on PortE Pins
(1)
Output
Output
Input
Input
I/O
Pull-up
Yes
No
No
No
Comment
Tri-state (High-Z)
PDn
if external pulled Low (default).
Push-pull zero output
Push-pull one output
(1)
will source current
Rev. 1138F–FPSLI–06/02

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