AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 162

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

FPSLIC Dual-port
SRAM
Characteristics
Frame Interface
162
AT94K Series FPSLIC
The Dual-port SRAM operates in single-edge clock controlled mode during read operations,
and a double-edge controlled mode during write operations. Addresses are clocked internally
on the rising edge of the clock signal (ME). Any change of address without a rising edge of ME
is not considered.
In read mode, the rising clock edge triggers data read without any significant constraint on the
length of the clock pulse. The WE signal must be changed and held Low before the rising
edge of ME to signify a read cycle. The WE signal should then remain Low until the falling
edge of the clock.
In write mode, data applied to the inputs is latched on either the falling edge of WE or the fall-
ing edge of the clock, whichever comes earlier, and written to memory. Also, WE must be High
before the rising edge of ME to signify a write cycle. If data inputs change during a write cycle,
only the value present at the write end is considered and written to the address clocked at the
ME rise. A write cycle ending on WE fall does not turn into a read cycle – the next cycle will be
a read cycle if WE remains Low during rising edge of ME.
Figure 83. SRAM Read Cycle Timing Diagram
Figure 84. SRAM Write Cycle Timing Diagram
The FPGA Frame Clock phase is selectable (see “System Control Register – FPGA/AVR” on
page 30). This document refers to the clock at the FPGA/Dual-port SRAM interface as ME (the
relation of ME to data, address and write enable does not change). By default, FrameClock is
inverted (ME = ~FrameClock). Selecting the non-inverted phase assigns ME = FrameClock.
Recall, the Dual-port SRAM operates in single-edge clock controlled mode during read opera-
tions, and double-edge clock controlled mode during writes. Addresses are clocked internally
on the rising edge of the clock signal (ME). Any change of address without a rising edge of ME
is not considered.
DATA READ
CLK (ME)
ADDR
DATA WRITE
WE
CLK (ME)
ADDR
WE
t
Previous Data
ADS
t
Address Valid
RDS
t
ADS
t
Address Valid
WRS
t
ADH
t
ACC
t
ADH
t
MEH
t
MPW
t
MPW
t
WDS
t
WDS
Data Valid
Output Valid
t
t
RDH
t
MEL
WDH
t
WDH
t
t
t
t
t
t
t
ADS
ADH
RDS
RDH
ACC
MEH
MEL
t
t
t
t
t
t
ADS
ADH
WRS
MPW
WDS
WDH
- Address Setup
- Address Hold
- Read Cycle Setup
- Read Cycle Hold
- Access Time from posedge ME
- Minimum ME High
- Minimum ME Low
- Address Setup
- Address Hold
- Write Cycle Setup
- Minimum Write Duration
- Data Setup to Write End
- Data Hold to Write End
Rev. 1138F–FPSLI–06/02