AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 24

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Data SRAM
Access by FPGA –
FPGAFrame Mode
SRAM Access
by FPGA/AVR
Accessing and
Modifying the
Program Memory
from the AVR
24
AT94K Series FPSLIC
The FPGA user logic has access to the data SRAM directly through the FPGA side of the
dual-port memory, see Figure 20. A single bit in the configuration control register (SCR63 –
see “System Control Register – FPGA/AVR” on page 30) enables this interface. The interface
is disabled during configuration downloads. Express buses on the East edge of the array are
used to interface the memory. Full read and write access is available. To allow easy imple-
mentation, the interface itself is dedicated in routing resources, and is controlled in the System
Designer software suite using the AVR FPGA interface dialog.
Figure 20. Internal SRAM Access – Normal Use
Once the SCR63 bit is set there is no additional read enable from the FPGA side. This means
that the read is always enabled. You can also perform a read or write from the AVR at the
same time as an FPGA read or write. If there is a possibility of a write address being accessed
by both devices at the same time, the designer should add arbitration to the FPGA Logic to
control who has priority. In most cases the AVR would be used to restrict access by the FPGA
using the FMXOR bit, see “Software Control Register – SFTCR” on page 51. You can read
from the same location from both sides simultaneously.
SCR bit 38 controls the polarity of the clock to the SRAM from the AT40K FPGA.
This option is used to allow for code (Program Memory) changes.
The FPSLIC SRAM is up to 36 x 8 Kbytes of dual port, see Figure 19):
•
•
•
Structurally, the [(n • 2) Kbytes 8] memory is built from (n)2 Kbytes 8 blocks, numbered
SRAM0 through SRAM(n).
The A side (port) is accessed by the AVR.
The B side (port) is accessed by the FPGA/Configuration Logic.
The B side (port) can be accessed by the AVR with ST and LD instructions in DBG mode
for code self-modify.
FPGA CORE
EMBEDDED
16 Address Lines:
FPGA Edge Express Buses
8-bit Data Read
8-bit Data Write
CLK FPGA
WE FPGA
SCR38
B Side A Side
16 Kbytes x 8
DATA SRAM
4 Kbytes x 8
UP TO
16-bit Data Address Bus
8-bit Data Read/Write
WE AVR
RE AVR
CLK AVR
Rev. 1138F–FPSLI–06/02
EMBEDDED
AVR CORE