AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 29

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AT94K05AL

Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet

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AVR Cache Mode
Resets
Rev. 1138F–FPSLI–06/02
The AVR has the ability to cache download the FPGA memory. The AVR has direct access to
the data buses of the FPGA’s configuration SRAM and is able to download bitstreams. AVR
Cache access of configuration SRAM is not available during normal configuration downloads.
The Cache Logic port in the AVR is located in the I/O memory map. Three registers, FPGAX,
FPGAY FPGAZ, control the address written to inside the FPGA; and FPGAD in the AVR mem-
ory map controls the Data. Registers FPGAX, FPGAY and FPGAZ are write only, see
Figure 23.
Figure 23. Internal FPGA Configuration Access
The AVR Cache Logic access mode is write only. Transfers may be aborted at any time due to
AVR program wishes or external interrupts.
The FPGA CHECK function is not supported by the AVR Cache mode.
A typical application for this mode is for the AVR to accept serial data through a UART for
example, and port it as configuration data to the FPGA, thereby affecting a download, or allow-
ing reconfigurable systems where the FPGA is updated algorithmically by the AVR. For more
information, refer to the “AT94K Series Configuration” application note available on the Atmel
web site, at: http://www.atmel.com/atmel/acrobat/doc2313.pdf.
The user must have the flexibility to issue resets and reconfiguration commands to separate
portions of the device. There are two Reset pins on the FPSLIC device. The first, RESET,
results in a clearing of all FPGA configuration SRAM and the System Control Register, and ini-
tiates a download if in mode 0. The AVR will stop and be reset.
A second reset pin, AVRReset, is implemented to reset the AVR portion of the FPSLIC func-
tional blocks. This is described in the “Reset Sources” on page 61.
interrupted during
(Operation is not
FPGA CORE
EMBEDDED
Cache Logic
loading)
Configuration Clock – Each tick is generated when the Memory-
mapped I/O location FPGAD is written to inside the AVR.
24-bit Address Write
Memory Write Data
8-bit Configuration
CACHEIOWE
Configuration Logic
AT94K Series FPSLIC
FPGAZ [7:0]
FPGAD [7:0]
FPGAX [7:0]
FPGAY [7:0]
Memory-mapped
Memory-mapped
Memory-mapped
Memory-mapped
EMBEDDED
Location
Location
Location
Location
AVR CORE
29

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