AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 51

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Software Control
of System
Configuration
Rev. 1138F–FPSLI–06/02
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program
before any subroutine calls are executed or interrupts are enabled. The stack pointer must be
set to point above $60. The Stack Pointer is decremented by one when data is pushed onto
the Stack with the PUSH instruction, and it is decremented by two when an address is pushed
onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two
when an address is popped from the Stack with return from subroutine RET or return from
interrupt RETI.
The software control register will allow the software to manage select system level configura-
tion bits.
Software Control Register – SFTCR
• Bits 7..4 - Res: Reserved Bits
These bits are reserved in the AT94K and always read as zero.
• Bit 3 - FMXOR: Frame Mode XOR (Enable/Disable)
This bit is XORed with the System Control Register’s Enable Frame Interface bit. The behavior
when this bit is set to 1 is dependent on how the SCR was initialized. If the Enable Frame
Interface bit in the SCR is 0, the FMXOR bit enables the Frame Interface when set to 1. If the
Enable Frame Interface bit in the SCR is 1, the FMXOR bit disables the Frame Interface when
set to 1. During AVR reset, the FMXOR bit is cleared by the hardware.
• Bit 2 - WDTS: Software Watchdog Test Clock Select
When this bit is set to 1, the test clock signal is selected to replace the AVR internal oscillator
into the associated watchdog timer logic. During AVR reset, the WDTS bit is cleared by the
hardware.
• Bit 1 - DBG: Debug Mode
When this bit is set to 1, the AVR can write its own program SRAM. During AVR reset, the
DBG bit is cleared by the hardware.
• Bit 0 - SRST: Software Reset
When this bit is set (one), a reset request is sent to the system configuration external to the
AVR. Appropriate reset signals are generated back into the AVR and configuration download
is initiated. A software reset will cause the EXTRF bit in the MCUR register to be set (one),
which remains set throughout the AVR reset and may be read by the restarted program upon
reset complete. The external reset flag is set (one) since the requested reset is issued from
the system configuration external to the AVR core. During AVR reset, the SRST bit is cleared
by the hardware.
Bit
$3A ($5A)
Read/Write
Initial Value
7
-
R
0
6
-
R
0
5
-
R
0
4
-
R
0
3
FMXOR
R/W
0
AT94K Series FPSLIC
2
WDTS
R/W
0
1
DBG
R/W
0
0
SRST
R/W
0
SFTCR
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