AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 52

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

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AT94K Series FPSLIC
MCU Control Status/Register – MCUR
The MCU Register contains control bits for general MCU functions and status bits to indicate
the source of an MCU reset.
• Bit 7 - JTRF: JTAG Reset Flag
This flag is set (one) upon issuing the AVR_RESET ($C) JTAG instruction. The flag can only
be cleared (zero) by writing a zero to the JTRF bit or by a power-on reset. The bit will not be
cleared by hardware during AVR reset.
• Bit 6 - JTD: JTAG Disable
When this bit is cleared (zero), and the System Control Register JTAG Enable bit is set (one),
the JTAG interface is disabled. To avoid unintentional disabling or enabling of the JTAG inter-
face, a timed sequence must be followed when changing this bit: the application software must
write this bit to the desired value twice within four cycles to change its value.
• Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep mode unless it is the program-
mers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of
the SLEEP instruction.
• Bits 4, 3 - SM1/SM0: Sleep Mode Select Bits 1 and 0
This bit selects between the three available Sleep modes as shown in Table 11.
• Bit 2 - PORF: Power-on Reset Flag
This flag is set (one) upon power-up of the device. The flag can only be cleared (zero) by writ-
ing a zero to the PORF bit. The bit will not be cleared by the hardware during AVR reset.
• Bit 1 - WDRF: Watchdog Reset Flag
This bit is set if a watchdog reset occurs. The bit is cleared by writing a logic 0 to the flag.
• Bit 0 - EXTRF: External (Software) Reset Flag
This flag is set (one) in three separate circumstances: power-on reset, use of Resetn/AVRRe-
setn and writing a one to the SRST bit in the Software Control Register – SFTCR. The PORF
flag can be checked to eliminate power-on reset as a cause for this flag to be set. There is no
way to differentiate between use of Resetn/AVRResetn and software reset. The flag can only
be cleared (zero) by writing a zero to the EXTRF bit. The bit will not be cleared by the hard-
ware during AVR reset.
Table 11. Sleep Mode Select
Bit
$35 ($55)
Read/Write
Initial Value
SM1
0
0
1
1
7
JTRF
R/W
0
6
JTD
R/W
0
5
SE
R/W
0
4
SM1
R/W
0
SM0
0
1
0
1
3
SM0
R/W
0
2
PORF
R/W
1
Sleep Mode
Idle
Reserved
Power-down
Power-save
1
WDRF
R/W
0
Rev. 1138F–FPSLI–06/02
0
EXTRF
R/W
1
MCUR