AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 54

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

54
AT94K Series FPSLIC
(FPGAIOWE
the FPGA I/O read/write enables, FPGAIORE or FPGAIOWE, to qualify each select line. The
FIADR bit will be cleared (zero) during AVR reset.
• Bits 6..2 - Res: Reserved Bits
These bits are reserved and always read as zero.
• Bits 1, 0 - XFIS1, 0: Extended FPGA I/O Select Bits 1, 0
XFIS[1:0] determines which one of the four FPGA I/O select lines will be set (one) within the
accessed group. An I/O read or write to one of the four dual-purpose I/O addresses, FISUA..D,
will access one of four groups. Table 12 details the FPGA I/O selection scheme.
Table 12. FPGA I/O Select Line Scheme
Note:
In summary, 16 select signals are sent to the FPGA for I/O addressing. These signals are
decoded from four base I/O Register addresses (FISUA..D) and extended to 16 with two bits
from the FPGA I/O Select Control Register, XFIS1 and XFIS0. The FPGA I/O read and write
signals, FPGAIORE and FPGAIOWE, are qualified versions of the AVR IORE and IOWE sig-
nals. Each will only be active if one of the four base I/O addresses is accessed.
Reset: all select lines become active and an FPGAIOWE strobe is enabled. This is to allow the
FPGA design to load zeros (8’h00) from the D-bus into appropriate registers.
Read or Write
I/O Address
FISUA $14 ($34)
FISUB $15 ($35)
FISUC $16 ($36)
FISUD $17 ($37)
1. Not available on AT94K05.
←
(1)
(1)
IOWE). FPGA macros utilizing one or more FPGA I/O select lines must use
XFIS1
FISCR Register
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
XFIS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
15..12
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
FPGA I/O Select Lines
11..8
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
7..4
Rev. 1138F–FPSLI–06/02
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
3..0