AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 67

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Idle Mode
Power-down Mode
Power-save Mode
Rev. 1138F–FPSLI–06/02
When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the Idle
mode, stopping the CPU but allowing UARTs, Timer/Counters, Watchdog 2-wire Serial and
the Interrupt System to continue operating. This enables the MCU to wake-up from external
triggered interrupts as well as internal ones like the Timer Overflow and UART Receive Com-
plete interrupts. When the MCU wakes up from Idle mode, the CPU starts program execution
immediately.
When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the
Power-down mode. In this mode, the external oscillator is stopped, while the external inter-
rupts and the watchdog (if enabled) continue operating. Only an external reset, a watchdog
reset (if enabled), or an external level interrupt can wake-up the MCU.
In Power-down and Power-save modes, the four external interrupts, EXT_INT0...3, and FPGA
interrupts, FPGA_INT0...3, are treated as low-level triggered interrupts.
If a level-triggered interrupt is used for wake-up from Power-down mode, the changed level
must be held for some time to wake-up the MCU. This makes the MCU less sensitive to noise.
The changed level is sampled twice by the watchdog oscillator clock, and if the input has the
required level during this time, the MCU will wake-up. The period of the watchdog oscillator is
1 µ s (n o m in a l) a t 3 .3 V a n d 2 5° C . T h e f re q u e n c y o f t h e w a t ch d o g o s ci lla to r is
voltage dependent.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same time-set bits that define the
reset time-out period. The wake-up period is equal to the clock reset period, as shown in
Figure 21 on page 89.
If the wake-up condition disappears before the MCU wakes up and starts to execute, the inter-
rupt causing the wake-up will not be executed.
When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power-save
mode. This mode is identical to power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. In addition to the power-down wake-up sources, the device can also
wake-up from either Timer Overflow or Output Compare event from Timer/Counter2 if the cor-
responding Timer/Counter2 interrupt enable bits are set in TIMSK. To ensure that the part
executes the Interrupt routine when waking up, also set the global interrupt enable bit in
SREG.
When waking up from Power-save mode by an external interrupt, two instruction cycles are
executed before the interrupt flags are updated. When waking up by the asynchronous timer,
three instruction cycles are executed before the flags are updated. During these cycles, the
processor executes instructions, but the interrupt condition is not readable, and the interrupt
routine has not started yet. See Table 2 on page 15 for clock activity during Power-down,
Power-save and Idle modes.
AT94K Series FPSLIC
67