AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 71

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Using the
Boundary-scan Chain
Using the On-chip
Debug System
Rev. 1138F–FPSLI–06/02
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is
•
•
•
•
As shown in Figure 40 on page 70, the Run-Test/Idle
selecting JTAG instruction and using Data Registers, and some JTAG instructions may select
certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note:
A complete description of the Boundary-Scan capabilities are given in the section “IEEE
1149.1 (JTAG) Boundary-scan” on page 73.
As shown in Figure 39, the hardware support for On-Chip Debugging consists mainly of
•
•
•
•
•
All read or modify/write operations needed for implementing the Debugger are done by apply-
ing AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an
I/O memory mapped location which is part of the communication interface between the CPU
and the JTAG system.
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the
Shift Instruction Register - Shift-IR state. While TMS is Low, shift the 4 bit JTAG
instructions into the JTAG instruction register from the TDI input at the rising edge of TCK,
while the captured IR-state 0x01 is shifts out on the TDO pin. The JTAG Instruction
selects a particular Data Register as path between TDI and TDO and controls the circuitry
surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is
latched onto the parallel output from the shift register path in the Update-IR state. The
Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register - Shift-DR state. While TMS is Low, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI
input at the rising edge of TCK. At the same time, the parallel inputs to the Data Register
captured in the Capture-DR state shifts out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state.
The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state
machine.
A scan chain on the interface between the internal AVR CPU and the internal peripheral
units
A breakpoint unit
A communication interface between the CPU and JTAG system
A scan chain on the interface between the internal AVR CPU and the FPGA
A scan chain on the interface between the internal Program/Data SRAM and the FPGA
1. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always
be entered by holding TMS High for 5 TCK clock periods.
AT94K Series FPSLIC
(1)
state need not be entered between
71