AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 8
AT94K05AL
Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet
1.AT94K05AL.pdf
(192 pages)
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Cell Connections
The Cell
8
AT94K Series FPSLIC
Figure 5(a) depicts direct connections between an FPGA cell and its eight nearest neighbors.
Figure 5(b) shows the connections between a cell five horizontal local buses (one per busing
plane) and five vertical local buses (one per busing plane).
Figure 5. Cell Connections
Figure 6 depicts the AT40K FPGA embedded core logic cell. Configuration bits for separate
muxes and pass gates are independent. All permutations of programmable muxes and pass
gates are legal. Vn is connected to the vertical local bus in plane n. Hn is connected to the hor-
izontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass
gates connected to Vn and Hn. Up to five simultaneous local/local turns are possible.
The logic cell can be configured in several “modes”. The logic cell flexibility makes the FPGA
architecture well suited to all digital design application areas, see Figure 7. The IDS layout tool
automatically optimizes designs to utilize the cell flexibility.
CELL
CELL
CELL
(a) Cell-to-Cell Connections
Y
X
X
CELL
CELL
CELL
Y
Y
X
X
Y
CELL
CELL
CELL
(b) Cell-to-Bus Connections
Rev. 1138F–FPSLI–06/02
W
X
Y
Z
L
WXYZL
CELL
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