AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 93

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
Table 25. PWM Outputs OCRn = $00 or $FF
Notes:
In up/down PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter
advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as in normal
Timer/Counter mode. Timer Overflow Interrupts 0 and 2 operate exactly as in normal
Timer/Counter mode, i.e. they are executed when TOV0 or TOV2 are set provided that Timer
Overflow Interrupt and global interrupts are enabled. This does also apply to the Timer Output
Compare flag and interrupt.
Asynchronous Status Register – ASSR
• Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the FPSLIC and are always read as zero.
• Bit 3 - AS2: Asynchronous Timer/Counter2 Mode
When this bit is cleared (zero) Timer/Counter2 is clocked from the internal system clock, CK. If
AS2 is set, the Timer/Counter2 is clocked from the TOSC1 pin. When the value of this bit is
changed the contents of TCNT2, OCR2 and TCCR2 might get corrupted.
• Bit 2 - TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set
(one). When TCNT2 has been updated from the temporary storage register, this bit is cleared
(zero) by the hardware. A logic 0 in this bit indicates that TCNT2 is ready to be updated with a
new value.
• Bit 1 - OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set
(one). When OCR2 has been updated from the temporary storage register, this bit is cleared
(zero) by the hardware. A logic 0 in this bit indicates that OCR2 is ready to be updated with a
new value.
• Bit 0 - TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set
(one). When TCCR2 has been updated from the temporary storage register, this bit is cleared
(zero) by the hardware. A logic 0 in this bit indicates that TCCR2 is ready to be updated with a
new value.
If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is
set (one), the updated value might get corrupted and cause an unintentional interrupt to occur.
Bit
$26 ($46)
Read/Write
Initial Value
COMn1
1. n overflow PWM mode, this table is only valid for OCRn = $FF
2. n = 0 or 2
1
1
1
1
(2)
7
-
R
0
6
-
R
0
COMn0
5
-
R
0
0
0
1
1
(2)
4
-
R
0
(1)
3
AS2
R/W
0
AT94K Series FPSLIC
OCRn
$FF
$FF
$00
$00
2
TCN2UB
R
0
(2)
1
OCR2UB
R
0
Output PWMn
0
TCR2UB
R
0
H
H
L
L
ASSR
(2)
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