AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 94

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Asynchronous
Operation of
Timer/Counter2
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AT94K Series FPSLIC
The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2,
the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary stor-
age register is read.
When Timer/Counter2 operates asynchronously, some considerations must be taken:
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When switching between asynchronous and synchronous clocking of Timer/Counter2, the
timer registers TCNT2, OCR2 and TCCR2 might get corrupted. A safe procedure for
switching the clock source is:
1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2 and TCCR2.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
5. Enable interrupts, if needed.
The oscillator is optimized for use with a 32.768 kHz watch crystal. An external clock
signal applied to this pin goes through the same amplifier having a bandwidth of 256 kHz.
The external clock signal should therefore be in the interval
0 Hz – 1 MHz. The frequency of the clock signal applied to the TOSC1 pin must be lower
than one fourth of the CPU main clock frequency.
When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to
a temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to
its destination. Each of the three mentioned registers have their individual temporary
register, which means that, e.g., writing to TCNT2 does not disturb an OCR2 write in
progress. To detect that a transfer to the destination register has taken place, an
Asynchronous Status Register – ASSR has been implemented.
When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the
user must wait until the written register has been updated if Timer/Counter2 is used to
wake-up the device. Otherwise, the MCU will go to sleep before the changes have had any
effect. This is extremely important if the Output Compare2 interrupt is used to wake-up the
device; Output compare is disabled during write to OCR2 or TCNT2. If the write cycle is
not finished (i.e., the MCU enters Sleep mode before the OCR2UB bit returns to zero), the
device will never get a compare match and the MCU will not wake-up.
If Timer/Counter2 is used to wake-up the device from Power-save mode, precautions must
be taken if the user wants to re-enter Power-save mode: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and reentering Power-save mode is
less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake up.
If the user is in doubt whether the time before re-entering power-save is sufficient, the
following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR2, TCNT2, or OCR2.
2. Wait until the corresponding Update Busy flag in ASSR returns to zero.
3. Enter Power-save mode.
When asynchronous operation is selected, the 32.768 kHz oscillator for Timer/Counter2 is
always running, except in Power-down mode. After a power-up reset or wake-up from
power-down, the user should be aware of the fact that this oscillator might take as long as
one second to stabilize. Therefore, the contents of all Timer2 registers must be considered
lost after a wake-up from power-down, due to the unstable clock signal. The user is
advised to wait for at least one second before using Timer/Counter2 after power-up or
wake-up from power-down.
Description of wake-up from Power-save mode when the timer is clocked asynchronously.
When the interrupt condition is met, the wake-up process is started on the following cycle
Rev. 1138F–FPSLI–06/02