AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 95
AT94K05AL
Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet
1.AT94K05AL.pdf
(192 pages)
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Timer/Counter1
Figure 54. Timer/Counter1 Block Diagram
Rev. 1138F–FPSLI–06/02
REGISTER (TIMSK)
15
15
15
15
TIMER INT. MASK
TIMER/COUNTER1 OUTPUT COMPARE REGISTER A
T/C1 OVER-
T/C1 INPUT CAPTURE REGISTER (ICR1)
FLOW IRQ
TIMER/COUNTER1 (TCNT1)
16 BIT COMPARATOR
•
Figure 54 shows the block diagram for Timer/Counter1.
T/C1 COMPARE
8
MATCHA IRQ
8
8
8
of the timer clock, that is, the timer is always advanced by at least one before the
processor can read the counter value. The interrupt flags are updated three processor
cycles after the processor clock has started. During these cycles, the processor executes
instructions, but the interrupt condition is not readable, and the interrupt routine has not
started yet.
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is
therefore advanced by at least one before the processor can read the timer value causing
the setting of the interrupt flag. The output compare pin is changed on the timer clock and
is not synchronized to the processor clock.
7
7
7
7
REGISTER (TIFR)
TIMER INT. FLAG
T/C1 COMPARE
MATCHB IRQ
CAPTURE
TRIGGER
0
0
0
0
REGISTER A (TCCR1A)
15
15
TIMER/COUNTER1 OUTPUT COMPARE REGISTER B
T/C CLEAR
T/C CLOCK SOURCE
UP/DOWN
T/C1 CONTROL
CAPTURE IRQ
T/C1 INPUT
16 BIT COMPARATOR
CONTROL
LOGIC
8
8
7
7
REGISTER B (TCCR1B)
AT94K Series FPSLIC
T/C1 CONTROL
0
0
SPECIAL FUNCTIONS
IO REGISTER (SFIOR)
CK
T1
95
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