AT94S05AL ATMEL Corporation, AT94S05AL Datasheet

AT94S05AL

Manufacturer Part Number

AT94S05AL

Description

The Secure Fpslic Combines Our AT94K05AL Fpslic Device And a Secure Configuration EePROM in a Single 256-pin Cabga Package.

Manufacturer

ATMEL Corporation

Datasheet

1.AT94S05AL.pdf (31 pages)

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AT94S05AL-25BQU

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AT94S05AL-25DGC

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Features

•

Multichip Module Containing Field Programmable System Level Integrated Circuit

(FPSLIC

512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

Programming (ISP)

Field Programmable System Level Integrated Circuit (FPSLIC)

5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM

Patented AVR Enhanced RISC Architecture

Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM

AVR Fixed Peripherals

Support for FPGA Custom Peripherals

Up to 16 FPGA Supplied Internal Interrupts to AVR

Up to Four External Interrupts to AVR

8 Global FPGA Clocks

Multiple Oscillator Circuits

5V Tolerant I/O

3.3V 33 MHz PCI Compliant FPGA I/O

High-performance, Low-power 0.35µ CMOS Five-layer Metal Process

State-of-the-art Integrated PC-based Software Suite including Co-verification

– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR

– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM

– High-performance DSP Optimized FPGA Core Cell

– Dynamically Reconfigurable In-System – FPGA Configuration Access Available

– Very Low Static and Dynamic Power Consumption – Ideal for Portable and

– 120+ Powerful Instructions – Most Single Clock Cycle Execution

– High-performance Hardware Multiplier for DSP-based Systems

– Approaching 1 MIPS per MHz Performance

– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers

– Low-power Idle, Power-save, and Power-down Modes

– 100 µA Standby and Typical 2-3 mA per MHz Active

– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM

– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM

– Industry-standard 2-wire Serial Interface

– Two Programmable Serial UARTs

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture

– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly

– FPGA Macro Library of Custom Peripherals

– Two FPGA Clocks Driven from AVR Logic

– FPGA Global Clock Access Available from FPGA Core

– Programmable Watchdog Timer with On-chip Oscillator

– Oscillator to AVR Internal Clock Circuit

– Software-selectable Clock Frequency

– Oscillator to Timer/Counter for Real-time Clock

– 20 mA Sink/Source High-performance I/O Structures

– All FPGA I/O Individually Programmable

: 3.0V - 3.6V

Extensive Data and Instruction SRAM

On-chip from AVR Microcontroller Core to Support Cache Logic

Handheld Applications

Modes and Dual 8-, 9- or 10-bit PWM

Accessible to FPGA

™

) and Secure Configuration EEPROM Memory

Designs

™

Core and

Secure

5K - 40K Gates

of AT40K FPGA

with 8-bit

Microcontroller,

up to 36 Kbytes

of SRAM and

On-chip

Program

Storage

EEPROM

AT94S

Secure Series

Programmable

SLI

Rev. 2314C–FPSLI–06/02

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