ICE1232 IC Ensemble, ICE1232 Datasheet - Page 24

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ICE1232

Manufacturer Part Number
ICE1232
Description
ac 97 2.1 VSR Audio Codec With 3D
Manufacturer
IC Ensemble
Datasheet

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Vendor Reserved Register (Index 5Ah)
Res.
IB[1:0]
Vendor Identification Register (Index 7Ch)
The upper and lower byte of this register (index 7Ch), in conjunction with the upper byte of index register 7Eh,
make up the vendor identification code for the ICE1232. The Vendor ID Code (in ASCII format) is equal to
ICE, where:
F[7:0]
S[7:0]
T[15:8]
Revision Identification Register (Index 7Eh)
The upper byte of this register is used in conjuction with index register 7Ch to make up the Vendor ID code for
the ICE1232. The lower byte identifies ICE1232 and its revision code.
T[15:8]
REV[7:0]
Note: As a reference, other valid IDs associated with ICE AC’97 products are: “01” for ICE1230.
24
D15
D15
D15
F7
T7
D14
D14
D14
F6
T6
D13
D13
D13
F5
T5
D12
Reserved
These read/write bits are used for testing the digital modes of the audio codec. Do not
access them during Normal operation.
Analog Current Setting Bits
Normally these bits should be left at default when analog operating at 5V supply. The four
possible settings adjust the power consumption of the analog section. The power-up
default 00b sets the codec for the best analog performance at 5V. At 3.3V analog supply,
10b should be set for the best analog performance instead of default 00b. Setting to 11b
puts the codec in its most aggressive low power consumption mode during normal
operation. This mode is desirable for system designs with limited power budget such as
battery operated portable devices. Intermediate steps 01b and 10b set the analog bias
current to 40% and 50% of maximum respectively. However it does not translate linearly
to the total analog power consumption current.
D12
Upper Byte (Index 7Ch) D[15:8] = I
Lower Byte (Index 7Ch) D[7:0] = C
Upper Byte (Index 7Eh) D[15:8] = E
D12
See description in Vendor Identification Register.
Revision ID
“11”:
F4
T4
D11
D11
D11
F3
T3
Revision Number
D10
D10
D10
F2
T2
D9
D9
D9
F1
T1
D8
D8
D8
F0
T0
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
Res.
D7
D7
D7
S7
Res.
D6
D6
D6
S6
Res.
D5
D5
D5
S5
Res.
D4
D4
D4
S4
IB1
D3
D3
S3
D3
IB0
D2
D2
D2
S2
Preliminary
D1
D1
D1
S1
Rev. 1.5, 1/10/00
Res.
D0
D0
D0
S0
Default
Default
Default
0021h
4943h
4511h

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