nRF24E1 Nordic VLSI, nRF24E1 Datasheet
nRF24E1
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nRF24E1 Summary of contents
Page 1
... Internal VDD monitoring Supplied in 36 pin QFN (6x6mm) package Mask programmable version available Very few external components Ease of design Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 1.0 Wireless gamepads Wireless headsets Wireless keyboards Wireless mouse Industrial sensors PC peripherals ...
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... Interrupt Latency from Power Down State. ....................................................49 7.8 Single-Step Operation .....................................................................................49 8 WAKEUP TIMER AND WATCHDOG...............................................................50 8.1 Tick calibration ...............................................................................................50 8.2 RTC Wakeup timer .........................................................................................50 8.3 Watchdog ........................................................................................................51 8.4 Reset................................................................................................................52 9 POWER SAVING MODES ..................................................................................53 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ!ÂsÃ(& July 2003 ...
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... Power down mode...........................................................................................54 10 MICROCONTROLLER.....................................................................................56 10.1 Memory Organization .....................................................................................56 10.2 Program format in external EEPROM ............................................................57 10.3 Instruction Set .................................................................................................58 10.4 Instruction Timing...........................................................................................64 10.5 Dual Data Pointers ..........................................................................................64 10.6 Special Function Registers..............................................................................65 10.7 SFR registers unique to nRF24E1...................................................................68 10.8 Timers/Counters..............................................................................................70 10.9 Serial Interface ................................................................................................78 11 ELECTRICAL SPECIFICATIONS ...................................................................87 12 PACKAGE OUTLINE.......................................................................................89 13 ABSOLUTE MAXIMUM RATINGS ...............................................................90 14 Peripheral RF Information..................................................................................91 15 Table of Figures ...
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... The nRF24E1 is a nRF2401 2.4GHz radio transceiver with an embedded 8051 compatible microcontroller and a 10-bit 9 input 100 kSPS AD converter. The circuit is supplied by only one voltage in range 1.9V to 3.6V. The nRF24E1 supports the proprietary and innovative modes of the nRF2401 such as ShockBurst™ and DuoCeiver™. ...
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... DVDD2 Power mgmt Regulators VDD Reset VSS SDO SCK SDI CSN 25320 EEPROM Figure 1-1 nRF24E1 block diagram plus external components Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 4k byte 512 byte 256 byte RAM ROM RAM ...
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... Digital I/O 5 P1.1 Digital I/O 6 P0.0 Digital I/O 7 P0.1/RXD Digital I/O 8 P0.2/TXD Digital I/O 9 P0.3/INT0_N Digital I/O 10 P0.4/INT1_N Digital I/O Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 QFN36 6x6 Power Supply (1.9-3.6 V DC) ADC input 0 Digital Power Supply , must be connected to ...
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... AIN1 Analog input 36 P1.2 Digital input Table 1-3 : nRF24E1 pin function Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Port 0, bit timer input or DIO7 Port 0, bit timer input or DIO8 Port 0, bit 7 or PWM output or DIO9 Digital voltage regulator output for ...
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... Receive SFR (8051) Special Function Register SPI Serial Peripheral Interface SPS Samples per Second ST_BY Standby TX Transmit XTAL Crystal (oscillator) Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ'ÂsÃ(& July 2003 ...
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... GPIO. The SFR (Special Function Registers) control several of the features of the nRF24E1. Most of the nRF24E1 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. The SFR map is shown in the table below. The registers with grey background are registers with industry standard 8051 behavior. Note that the function of P0 and P1 are somewhat different from the “ ...
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... XTAL oscillator. The duty cycle is programmable between 0% and 100% via one 8-bit register. nRF24E1 features a simple single buffered SPI master. The 3 lines of the SPI bus (SDI, SCK and SDO) are multiplexed (by writing to register SPI_CTRL) between the GPIO pins (P1.2/DIN0, P1.0/DIO0 and P1.1/DIO1) and the RF transceiver. The SPI hardware does not generate any chip select signal ...
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... The device can exit the power down mode by an external pin interrupt (INT0_N or INT1_N) if enabled, by the wakeup timer if enabled watchdog reset. The nRF24E1 contains a low power RC oscillator which can not be disabled will run continuously as long as VDD RTC Wakeup Timer and Watchdog are two 16 bit programmable timers that run on the RC oscillator LP_OSC clock. The resolution of the watchdog and wakeup timer is programmable from approximately 300µ ...
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... RX mode. For power saving the transceiver can be turned on / off under software control. Further information about the nRF2401 chip can be found at our website Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Qhtrà !ÂsÃ(& ...
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... PRODUCT SPECIFICATION The nRF24E1 have two IO ports located at the default locations for P0 and P1 in standard 8051, but the ports are fully bi-directional CMOS and the direction of each pin is controlled by a _DIR and an _ALT bit for each bit as shown in the table below. ...
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... Table 3-3 : Port 0 control and data SFR-registers The P1 port consists of only 3 pins, one of which is an hardwired input. The function is controlled by SPI_CTRL. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 P0.0 In P0.0 RXD In P0.1 TXD Out P0.2 INT0_N In P0 ...
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... Table 3-4 : Port 1 (P1) functions If SPI_CTRL is ‘01’, the P1 port is used as SPI master data and clock : 2 -> MISO – input to nRF24E1 from slave 1 -> MOSI – output from nRF24E1 to slave 0 -> SCK – output from nRF24E1 to slave Qhtrà $ÂsÃ(& P1.0 Out P1.1 Out P1 ...
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... R SPICLK Table 3-6 : SPI control and data SFR-registers Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 00 -> SPI not used no clock generated 01 -> SPI connected to port P1 (as for booting) another GPIO must be used as chip select (see also Table 3-4 : Port 1 (P1) functions) 10 -> ...
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... DR1, data ready from receiver 1 (available also as interrupt) 1: CLK1, clock for receiver 1 data out 0: DATA, data out from receiver 1 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 RADIO General purpose IO for interface to nRF2401 radio transceiver subsystem SPI_CTRL 00 -> ...
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... RADIO_wr.3 (CS) for Configuration SCK nRF2401/CLK1 SDI nRF2401/DATA SDO nRF2401/DATA ShockBurst™ data RADIO_rd.2 (DR1) ready Table 4-3 : Transceiver SPI interface. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 PWR_UP CE CLK2 CS DATA SPI_CTRL=11 RADIO_wr.6 (CE) nRF2401/CLK2 nRF2401/DOUT2 not used RADIO_rd ...
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... Active (RX/TX) Configuration Stand by Power down Table 4-4 nRF2401 subsystem main modes The nRF2401 subsystem has two active (RX/TX) modes: ShockBurst™ Direct Mode (not supported by nRF24E1) Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 SPI_CTRL MUX 3 MUX 2 ...
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... Mbps) offered by the 2.4 GHz band without the need of a costly, high- speed microcontroller (MCU) for data processing. By putting all high speed signal processing related to RF protocol on-chip, the nRF24E1 offers the following benefits: Highly reduced current consumption Lower system cost (facilitates use of less expensive microcontroller) Greatly reduced risk of ‘ ...
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... PRODUCT SPECIFICATION Without ShockBurst 10mA period Figure 4-3 RF Current consumption with & without ShockBurst technology Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 running at speed dictated by 10Kbs MCU 10mA period TM 10Kbs MCU with ShockBurst 80 100 ...
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... RF front end is powered up RF package is completed (preamble added, CRC calculated) Data is transmitted at high speed (250 kbps or 1 Mbps configured by user). nRF2401 subsystem returns to stand-by when finished Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Data content of registers: ADDR PAYLOAD ...
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... NO nRF2401 Register Empty? YES nRF2401 Sets Data Ready (DR1/2) low Figure 4-5 Flow Chart ShockBurst™ Receive of nRF2401 subsystem Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Data content of registers: Pre- ADDR PAYLOAD amble ADDR PAYLOAD ADDR ...
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... Figure 4-6 Simultaneous 2 channel receive on nRF24E1 There is one absolute requirement for using the second data channel. For the nRF24E1 to be able to receive at the second data channel the frequency channel must be 8MHz higher than the frequency of data channel 1. The nRF2401 subsystem must be Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... This enables the nRF2401 subsystem to distinguish between address and payload data. Address (RX Channel 1 and 2): Destination address for received data. CRC: Enables on-chip CRC generation and de-coding. NOTE: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Clock ADDR, Recovery, ...
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... ADDRESS Figure 4-8Data packet set-up For direct mode operation only the two first bytes (bit[15:0]) of the configuring word are relevant. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 PAYLOAD QhtrÃ!%ÂsÃ(& CRC ...
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... VDD is applied. Once the wanted protocol, modus and RF channel are set, only one bit (RXEN) is shifted in to switch between RX and TX. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Reserved for testing ...
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... OD XO Frequency Table 4-6 Configuration data word The MSB bit should be loaded first into the configuration register. Default configuration word: h8E08.1C20.2000.0000.00E7.0000.0000.E721.0F04. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 D138 D137 D136 Default TEST ...
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... CRC: check sum bits set in configuration word B[17] PRE: preamble bits are automatically included Shorter address and CRC leaves more room for payload data in each package. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 0 Open TX/Closed RX ...
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... Logic 1: On-chip CRC generation/checking enabled NOTE bit CRC will increase the number of payload bits possible in each ShockBurst™ data packet, but will also reduce the system integrity. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... RX2_EN: Logic 0: One channel receive Logic 1: Two channels receive NOTE: In two channels receive, the nRF24E1 receives on two, separate frequency channels simultaneously. The frequency of receive channel 1 is set in the configuration word B[7-1], receive channel 2 is always 8 channels (8 MHz) above receive channel 1. Bit 14: Communication Mode: Logic 0: nRF2401 subsystem operates in direct mode ...
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... RF_PWR: Sets nRF24E1 RF output power in transmit mode: Table 4-13 RF output power setting. 4.3.4.2.2 RF channel & direction 7 6 Table 4-14 Frequency channel + setting. Bit 7 – 1: RF_CH#: Sets the frequency channel the nRF24E1 operates on. The channel frequency in 2400 5) RF_CH #: between 2400MHz and 2527MHz may be set. The channel frequency in 2400 5) RF_CH #: between 2400MHz and 2524MHz may be set ...
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... The data packet for both ShockBurst™ mode and direct mode communication is divided into 4 sections. These are: Table 4-15 Data package description Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 PAYLOAD The preamble field is required in ShockBurst™ and Direct modes Preamble is 8 (or 4) bits in length and is dependent of the first data bit of the address ...
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... PWR_UP CS CE CLK1 DATA Figure 4-10 Timing diagram for power down (or VDD off) to stand by mode for nRF2401 subsystem. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 3ms 3ms 195 s 202 ...
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... CE and CS may not be high at the same time. Setting one or the other decides whether configuration or active mode is entered. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Tpd2a Qhtrà ...
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... CS CE CLK1 DATA Figure 4-12 Timing diagram for configuration of nRF2401 subsystem If configuration mode is entered from power down, CS can be set high after Tpd2sby as shown in Figure 4-10. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 ‡Ã2à CLK1 ...
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... The package length and the data rate give the delay Toa (time on air), as shown in the equation. Databits are the total number of bits, including any CRC and preamble bits which may be added Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 CLK1 DATA ...
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... Figure 4-14 Timing of ShockBurst™ The CE may be kept high during downloading of data, but the cost is higher current consumption (18mA) and the benefit is no start-up time (200 s) after the DR1 goes low. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 hmin Qhtrà ...
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... ADCSTATIC (0xA4) contains infrequently used control functions that will normally not be changed by nRF24E1 applications. The high part of the result is available in the ADCDATAH (0xA2) register, whereas the ADCDATAL (0xA3) will hold the low part of the result (if any) and the end of conversion together with overflow status bits ...
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... CLK8 0 : ADC clock frequency = CPU clock divided ADC clock frequency = CPU clock divided – 2 ADCBIAS Control A/D converter bias current No need to change for nRF24E1 operation ADCRES Select A/D converter resolution 00: 6-bit, result in ADCDATAH 5-0 01: 8-bit, result in ADCDATAH 10: 10-bit, result in ADCDATAH,ADCDATAL.7-6 11: 12-bit, result in ADCDATAH,ADCDATAL.7-4 Table 5-2 : ADCSTATIC register, SFR 0xA4, default initial data value is 0x0A ...
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... This mode of operation is normally selected for sources where the voltage is depending on the supply voltage (or another variable voltage), like shown in Figure 5-2 below. The resistor R1 is selected to keep AREF voltage. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 ), the result in ADCDATAx is directly proportional to 7 ...
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... ADCDATAx is thus directly proportional to the VDD voltage. VDD voltage = 3. ADCDATA / 2**N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the result bits in ADCDATAH (and ADCDATAL if N > 8). Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 SUPPLY VDD ...
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... PRODUCT SPECIFICATION The nRF24E1 PWM output is a one-channel PWM with a 2 register interface. The first register, PWMCON, enables PWM function and PWM period length, which is the number of clock cycles for one PWM period, as shown in the table below. The other register, PWMDUTY, controls the duty cycle of the PWM output signal. When this register is written, the PWM signal will change immediately to the new value ...
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... Internal RADIO.DR1 interrupt (a packet is ready from receiver 1) int5 Internal RADIO.DR2 interrupt (a packet is ready from receiver 2) wdti Internal RTC wakeup timer interrupt Table 7-1 : nRF24E1 interrupt sources The following SFRs are associated with interrupt control – SFR 0xA8 ( Table 7 – SFR 0xB8 ( ) Table 7-3 - EXIF – ...
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... IE3 - Interrupt 3 flag. IE3 = 1 indicates that the internal SPI module has sent or received 8 bits, and is ready for a new command. IE3 must be cleared by software. Setting IE3 in software generates an interrupt, if enabled. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ#$ÂsÃ(& July 2003 ...
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... EX2 = 1 enables interrupts generated by the ADC_EOC signal. Table 7-6 : EIE Register – SFR 0xE8 explains the bit functions of the EIP register. Table 7-7 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ#%ÂsÃ(& July 2003 ...
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... SPI_READY interrupt int4 RADIO.DR1 interrupt int5 RADIO.DR2 interrupt wdti RTC wakeup timer interrupt Table 7-8 : Interrupt Natural Vectors and Priorities Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Natural Interrupt Priority Vector (lowest number gives highest priority) ...
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... INT0_N and int2 are both programmed as high priority, INT0_N takes precedence. Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 provides a summary of interrupt sources, Flag Enable TCON ...
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... DIV or MUL, and four to execute the LCALL to the ISR. For the maximum latency case, the response time =52clock cycles. nRF24E1 may be set into Power Down state by writing 0x2 or 0x3 to SFR 0xB6, register CK_CTRL. The CPU will then perform a controlled shutdown of clock and power regulator ...
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... The counter may be disabled again by writing a disable opcode to the control register. Both the latch and the counter value may be read by giving the respective codes in the control register, see description in Table 8-2 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Name ...
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... The nRF24E1 do not provide any “absolute time functions”. Absolute time functions in nRF24E1 can well be handled in software since our RAM is continuously powered even when in sleep mode. There will be an application note with the required code to implement the complete absolute time function using some 100 bytes of code and 12 IRAM locations (with 2 alarms) ...
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... REGX_ CTRL Table 8-2 : RTC and Watchdog SFR-registers nRF24E1 can be reset either by the on-chip power-on reset circuitry or by the on-chip watchdog counter. The power-on reset circuitry keeps the chip in power-on-reset state until the supply voltage reaches VDDmin. At this point the internal voltage generators and oscillators ...
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... PRODUCT SPECIFICATION If the Watchdog reset signal goes active, nRF24E1 enters the same reset sequence as for power-on reset, that is the internal voltage generators and oscillators start up, the SFRs are initialized to their reset values, as listed in Table 10-10, and thereafter the CPU begins program execution at the standard reset vector address 0x0000. The startup time from watchdog reset is somewhat shorter, 12 LP_OSC cycles, which in total may vary from 2 ...
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... CK_CTRL.1 bit and terminate power down mode. The CPU executes the ISR associated with the received interrupt. The RETI instruction at the end of the of ISR returns the CPU to the instruction following the one that put the nRF24E1 into power down mode. A watchdog reset causes the nRF24E1 to exit power down mode, reset internal registers, execute its reset sequence and begin program execution at the standard reset vector address 0x0000 ...
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... CK_CTRL .0 Not used CK_CTRL .1 STOP_CLOCK. Setting the STOP_CLOCK bit places the nRF24E1 in power down mode. Table 9-2 : CK_CTRL register - SFR 0xB6 Startup time consists of a number of LP_OSC cycles + a number of XTAL clock cycles. f may vary from 1 to 5.5kHz over voltage and temperature, but can be LP_OSC measured as described on page 50 ...
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... Memory (ERAM) Figure 10-1 : Memory Map and Organization The nRF24E1 has 4KB of program memory available for user programs located at the bottom of the address space as shown in Figure 10-1. This memory also function as a random access memory and can be accessed with the movx and movc instructions. ...
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... XO_FREQ (bits 2,1 and 0): Crystal oscillator frequency 000 = 4MHz, 001 = 8MHz, 010 = 12MHz, 011 = 16MHz, 100 = 20MHz The program eeprep can be used to add this header to a program file. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 Reserved SPEED (now 00) Qhtrà ...
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... However, the timing of the instructions is different, both in terms of number of clock cycles per instruction cycle and timing within the instruction cycle. Table 10-3 to Table 10-8 lists the nRF24E1 instruction set and the number of instruction cycles required to complete each instruction. Symbol ...
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... Increment data pointer MUL AB Multiply DIV AB Divide Decimal adjust A All mnemonics are copyright © Intel Corporation 1980. Table 10-3 : nRF24E1 Instruction Set, Arithmetic Instructions. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry All mnemonics are copyright © Intel Corporation 1980. Table 10-4 : nRF24E1 Instruction Set, Logical Instructions. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... OR direct bit inverse to carry MOV C, bit Move direct bit to carry MOV bit, C Move carry to direct bit All mnemonics are copyright © Intel Corporation 1980. Table 10-5 : nRF24E1 Instruction Set, Boolean Instructions. MOV A, Rn Move register to A MOV A, direct Move direct byte to A MOV A, @Ri ...
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... Exchange A and data memory nibble All mnemonics are copyright © Intel Corporation 1980. Table 10-6 : nRF24E1 Instruction Set, Data Transfer Instructions. * Number of cycles CKCON.2-0. (CKCON.2-0 is the integer value of the 3LSB of SFR 0x8E CKCON). Default is 3 cycles. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... Table 10-7 : nRF24E1 Instruction Set, Branching Instructions. NOP No operation There is an additional reserved opcode (A5) that performs the same function as All mnemonics are copyright © Intel Corporation 1980. Table 10-8 : nRF24E1 Instruction Set, Miscellaneous Instructions. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... This translates improvement in execution time for most instructions. However, some instructions require a different number of instruction cycles on the nRF24E1 than they do on the standard 8051. In the standard 8051, all instructions except for MUL and DIV take one or two instruction cycles to complete ...
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... Most of the nRF24E1 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. Table 10-9 lists the nRF24E1 SFRs and indicates which SFRs are not included in the standard 8051 SFR space. When writing software for the nRF24E1, use equate statements to define the SFRs that are specific to the nRF24E1 and custom peripherals ...
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... B 0xF8 EIP(1) 1 0xFE HWREV 0xFF ----- Table 10-9 Special Function Registers summary Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Bit 6 Bit 5 Bit 4 Bit 3 Port 0 Stack pointer Data pointer 0, low byte Data pointer 0, high byte Data pointer 1, low byte ...
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... TL2 0xCC 0x00 TMOD 0x89 0x00 Table 10-10 Special Function Register reset values and description, alphabetically. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Description Accumulator register Table 5-1, page 40 Table 5-3, page 41 Table 5-3, page 41 Table 5-2, page 40 B-register ...
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... Table 10-11 : PSW Register – SFR 0xD0 The table below lists the SFR registers that are unique to nRF24E1 (not part of standard 8051 register map) The registers P0, P1 and RADIO use the addresses for the ports P0, P1 and standard 8051. Whereas the functionality of these ports is similar to that of the corresponding ports in standard 8051 not identical ...
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... Table 10-12 : SFR registers unique to nRF24E1 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 RADIO General purpose IO for interface to 2401 radio, for details see ch. 4 nRF2401 2.4GHz TRANSCEIVER ADCCON ADC control register ADCDATAH High 8 bits of ADC result ...
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... PRODUCT SPECIFICATION The nRF24E1 includes three timer/counters (Timer 0, Timer 1 and Timer 2). Each timer/counter can operate as either a timer with a clock rate based on the CPU clock , event counter clocked by the t0 pin (Timer 0), t1 pin (Timer 1), or the t2 pin (Timer 2). These pins are alternate function bits of Port 0 and 1 as this : t0 is P0. ...
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... INT1_N pin is low and cleared when the INT1_N pin is high. In level-sensitive mode, software cannot write to IE1. TCON.2 IT1 - Interrupt 1 type select. When IT1 = 1, the nRF24E1 detects external interrupt pin INT1_N on the falling edge (edge-sensitive). When IT1 = 0, the nRF24E1 detects INT1_N as a low level (level-sensitive). ...
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... As illustrated in Figure 10-3 : Timer 0/1 – Mode 2, mode 2 counter control is the same as for mode 0 and mode 1. However, in mode 2, when TL increments from 0xFF, the value stored reloaded into TLn. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ&!ÂsÃ(& ...
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... C/T bit. The GATE function can be used to give counter enable control to the INT0_N signal. Figure 10-4 : Timer 0 – Mode 3 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ&"ÂsÃ(& July 2003 ...
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... The Timer 1 GATE function is also available when Timer mode 3. The default timer clock scheme for the nRF24E1 timers is twelve CPU clock cycles per increment, the same as in the standard 8051. However, in the nRF24E1, the instruction cycle is four clock cycles. Using the default rate (twelve clocks per timer increment) allows existing application code with real-time dependencies, such as baud rate, to operate properly ...
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... Table 10-16 : T2CON Register – SFR 0xC8 10.8.3.1 Timer 2 Mode Control Table 10-17 summarizes how the SFR bits determine the Timer 2 mode. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ&$ÂsÃ(& July 2003 ...
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... TH2. The software must preload the starting value into the RCAP2L and RCAP2H registers. When Timer auto-reload mode, a reload can be forced by a high-to-low transition on the t2ex pin, if enabled by EXEN2 = 1. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 TR2 Mode ...
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... CPU_clk/2. To use an external clock source, set C/ and apply the desired clock source to the t2 pin. Figure 10-7 : Timer 2 – Baud Rate Generator Mode Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ&&ÂsÃ(& ...
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... PRODUCT SPECIFICATION The nRF24E1 is configured with one serial port, which is identical in operation to the standard 8051 serial port. The two serial port pins rxd and txd are available as alternate functions of P0.1 and P0.2, for details please see ch. 3 I/O PORTS. The serial port can operate in synchronous or asynchronous mode. In synchronous mode, the nRF24E1 generates the serial clock and the serial port operates in half- duplex mode ...
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... The Port 0, please also see Table 3-2 : Port 0 (P0) functions for port and pin configuration. The lack of open drain ports on nRF24E1 makes it a programmer responsibility to control the direction of the rxd pin. The serial mode 0 baud rate is either CPU_clk/12 or CPU_clk/4, depending on the state of the SM2. When SM2 = 0, the baud rate is CPU_clk/12 ...
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... Therefore, when using Timer 1, the baud rate is determinedby the equation: 2 Baud Rate = x Timer 1 Overflow 32 SMOD is SFR bit PCON.7 When using Timer 2, the baud rate is determined by the equation: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ'ÂsÃ(& July 2003 ...
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... CPU_clk signal to be divided shown in Figure 10-7 : Timer 2 – Baud Rate Generator Mode, instead of the determined by the T2M bit in the CKCON SFR. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 clk ...
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... SBUF register. The UART transmits data on the txd pin in the following order: start bit, eight data bits (LSB first), stop bit. The TI bit is set two clock cycles after the stop bit is transmitted. Figure 10-12 : Serial port Mode 1 Transmit Timing Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... Mode 2 provides asynchronous, full-duplex communication, using a total of eleven bits: - One start bit - Eight data bits - One programmable 9th bit Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 For this purpose, When a falling edge of a QhtrÃ'"ÂsÃ(& ...
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... Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ'#ÂsÃ(& ...
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... Figure 10-16 illustrates the mode 3 transmit timing. Mode 3 operation is identical to that of the standard 8051 when Timers 1 and 2 use CPU_clk/12 (the default). Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ'$ÂsÃ(& ...
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... The addressed slave clears its SM2 bit and prepares to receive the data bytes. The slaves that are not being addressed leave the SM2 bit set and ignore the incoming data bytes. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 th bit to 1 ...
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... SNR Signal to Noise Ratio (without harmonics kHz IN SFDR Spurious Free Dynamic Range f V Internal reference BG Internal reference voltage drift Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 40º 85ºC A 1.9 -40 VDD- 0.3 Vss =-0.5mA) VDD- 0 ...
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... NOTES: 1) Usable band is determined by local regulations 2) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in the nRF2401 configuration word, please seeTable 14-2 Crystal specification of the nRF24E1. 16MHz is required for 1Mbps operation. 3) Current for nRF2401 subsystem only. 4) ...
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... PRODUCT SPECIFICATION nRF24E1 uses the QFN 36LD 6x6 package. Dimensions are in mm. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ'(ÂsÃ(& July 2003 ...
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... PRODUCT SPECIFICATION QFN36 0.8 0.0 (6x6 mm) 1 0.05 Figure 12-1 : nRF24E1 package outline. VDD ............................- 0. 3.6V VSS .................................................. 0V V .......................- 0.3V to VDD + 0. ......................- 0.3V to VDD + 0. =85 C).............................. 60mW D A Operating Temperature… Storage Temperature….… 125 C Electrostatic Sensitive Device Observe Precaution for handling. Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1 ...
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... Lower load impedance (for instance 50 ) can be obtained by fitting a simple matching network Conditions: VDD = 3.0V, VSS = 0V, T Table 14-1 RF output power setting for the nRF24E1. Tolerance includes initially accuracy and tolerance over temperature and aging MHz 12pF 8 MHz 12pF 12 MHz ...
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... PRODUCT SPECIFICATION Figure 1-1 nRF24E1 block diagram plus external components .....................................5 Figure 4-1 : Transceiver interface ................................................................................19 Figure 4-2Clocking in data with CPU and sending with ShockBurst technology ....20 Figure 4-3 RF Current consumption with & without ShockBurst technology..........21 Figure 4-4 Flow Chart ShockBurst™ Transmit of nRF2401 subsystem .....................22 Figure 4-5 Flow Chart ShockBurst™ Receive of nRF2401 subsystem .......................23 Figure 4-6 Simultaneous 2 channel receive on nRF24E1 ...
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... Table 10-3 : nRF24E1 Instruction Set, Arithmetic Instructions...................................59 Table 10-4 : nRF24E1 Instruction Set, Logical Instructions........................................60 Table 10-5 : nRF24E1 Instruction Set, Boolean Instructions.......................................61 Table 10-6 : nRF24E1 Instruction Set, Data Transfer Instructions..............................62 Table 10-7 : nRF24E1 Instruction Set, Branching Instructions. ..................................63 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Qhtrà ...
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... Table 10-20 : Timer 1 Reload Values for Serial Port Mode 1 Baud Rates ..................81 Table 10-21 : Timer 2 Reload Values for Serial Port Mode 1 Baud Rates ..................82 Table 11-1 : nRF24E1 Electrical specifications...........................................................88 Table 14-1 RF output power setting for the nRF24E1.................................................91 Table 14-2 Crystal specification of the nRF24E1. .......................................................91 Table 17-1 :Definitions ................................................................................................95 Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 Qhtrà ...
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... Nordic VLSI ASA for any damages resulting from such improper use or sale. Preliminary Product Specification: Revision Date: 01.07.2003. Datasheet order code: 010703-nRF24E1. All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. ...
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... PRODUCT SPECIFICATION Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ(%ÂsÃ(& July 2003 ...
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... PRODUCT SPECIFICATION Vestre Rosten 81, N-7075 Tiller, Norway Phone: + 00, Fax: + Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.0 QhtrÃ(&ÂsÃ(& July 2003 ...