AT91FR40162S ATMEL Corporation, AT91FR40162S Datasheet
AT91FR40162S
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AT91FR40162S Summary of contents
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... Available in a 121-ball 1.2 mm BGA Package with 0.8 mm Ball Pitch 1. Description The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption ...
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... Pin Configuration Figure 2-1. AT91FR40162S Pinout for 121-ball BGA Package (Top View) A1 Corner 1 P21/TXD1 NTRI P22 RXD1 VDDIO P23 P24 BMS GND TDO P26 NCS2 NWAIT NCS1 GND AT91FR40162S 2 4 DataSheet U .com P15 P11 P19 P16 GND RXD0 IRQ2 ...
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... Pin Description Table 3-1. AT91FR40162S Pin Description Module Name A0 - A23 D0 - D15 NCS0 - NCS3 CS4 - CS7 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BMS FIQ AIC IRQ0 - IRQ2 TCLK0 - TCLK2 Timer TIOA0 - TIOA2 TIOB0 - TIOB2 SCK0 - SCK1 USART TXD0 - TXD1 ...
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... Table 3-1. AT91FR40162S Pin Description (Continued) Module Name NCSF Flash NBUSY Memory NRSTF VDDIO VDDCORE Power GND VPP AT91FR40162S 4 4 DataSheet U .com Function Type Flash Memory Select Input Flash Memory Busy Output Output Flash Memory Reset Input Input Power Power Power ...
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... Block Diagram Figure 4-1. AT91FR40162S 6174AS–ATARM–25-May-05 4 DataSheet U .com Interface Bus External EBI: AT91FR40162S 5 ...
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... Memories The AT91FR40162S embeds 256K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum per- formance of 67 MIPS at 75 MHz by using the ARM instruction set of the processor, minimizing system power consumption and improving on the performance of separate memory solutions ...
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... The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. The TC has also 3 exter- nal clock signals. 6174AS–ATARM–25-May-05 4 DataSheet U .com AT91FR40162S 7 ...
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... An independent I/O supply allows a flexible adaptation to external component signal levels. 6.2 Input/Output Considerations The AT91FR40162S I/O pads accept voltage levels up to the VDDIO power supply limit. After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility recommended that in any application phase, the inputs to the micro- controller be held at valid logic levels to minimize the power consumption ...
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... In any of these address spaces, the ARM7TDMI operates in little-endian mode only. 6.6.1 Internal Memories The AT91FR40162S microcontroller integrates 256K bytes of internal SRAM bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is supported, and internal memory can store two times as many Thumb instructions as ARM instructions ...
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... The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91FR40162S uses a remap command that enables switching between the boot memory and the internal primary SRAM bank addresses. ...
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... The External Bus Interface features also the Early Read Protocol, configurable for all the devices, that significantly reduces access time requirements on an external device in the case of single-clock cycle access. In the AT91FR40162S, the External Bus Interface connects internally to the Flash memory. 6.6.6 Flash Memory The 2-Mbyte Flash memory is organized as 1, 048, 576 words of 16 bits each ...
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... Flash Memory Uploader Operations The Flash Memory Uploader requires the encapsulated Flash to be used as the AT91FR40162S boot memory and a valid clock to be applied to MCKI. After reset, the Flash Memory Uploader immediately recopies itself into the internal SRAM and jumps to it. The fol- lowing operation requires this memory resource only ...
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... Note that in the event that the Flash Memory Uploader is erased from the first sector while the new final application is not yet programmed, and while the target system power supply is switched off, it leads to a non-recoverable error and the AT91FR40162S cannot be re-pro- grammed by using the Flash Memory Uploader. ...
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... Peripheral Data Controller The AT91FR40162S has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Reg- ister (RCR or TCR) ...
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... TC: Timer Counter The AT91FR40162S features a Timer Counter block that includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. ...
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... Ordering Information Table 7-1. Ordering Information Ordering Code AT91FR40162S-CJ AT91FR40162S 16 4 DataSheet U .com Package Package Type BGA 121 RoHS Temperature Operating Range Industrial (- 6174AS–ATARM–25-May-05 ...
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... Revision History Doc. Rev. Date 6174AS 25-May-05 6174AS–ATARM–25-May-05 4 DataSheet U .com Comments First issue. Qualified on the web AT91FR40162S Change Request Ref. 17 ...
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... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Windows others, are registered trademarks of ARM,Limited ...