AT91SAM7S256 ATMEL Corporation, AT91SAM7S256 Datasheet
AT91SAM7S256
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AT91SAM7S256 Summary of contents
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... Programmable Data Length, Four External Peripheral Chip Selects ® ® Thumb Processor AT91 ARM Thumb Microcontrollers AT91SAM7S256 Summary Preliminary Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office. ® ® ...
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... Description AT91SAM7S256 Summary Preliminary 2 Atmel’s AT91SAM7S256 is a member of a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 256 Kbyte high-speed Flash and a 64 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a com- plete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional per- formance and extended memory ...
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... Block Diagram Figure 1. AT91SAM7S256 Block Diagram TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 ...
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... Command NRST Microcontroller Reset TST Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input AT91SAM7S256 Summary Preliminary 4 Active Type Level Power Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs ...
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... PWM Channels MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 SPI Peripheral Chip Select 0 NPCS1-NPCS3 SPI Peripheral Chip Select 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary Active Type Level PIO I/O USB Device Port Analog Analog USART I/O I/O ...
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... Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK Programming Clock PGMNCMD Programming Command AT91SAM7S256 Summary Preliminary 6 Type Two-Wire Interface I/O I/O Analog-to-Digital Converter Analog Analog Input Analog Fast Flash Programming Interface Input Input I/O ...
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... PA20/PGMD8/AD3 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary The AT91SAM7S256 is available in a 64-lead LQFP package. Figure 2 shows the orientation of the 64-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 2. 64-lead LQFP Package Pinout (Top View) ...
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... The AT91SAM7S256 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current ...
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... Schematics 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary The AT91SAM7S256 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 3 shows the power schematics to be used for USB bus-powered systems. Figure 3. 3.3V System Single Power Supply Schematic ...
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... GND, so that it can be left unconnected for normal operations. The pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S256 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. ...
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... Processor and Architecture ARM7TDMI Processor Debug and Test Features Memory Controller 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets ® – ARM high-performance 32-bit instruction set ® ...
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... Peripheral Data Controller AT91SAM7S256 Summary Preliminary 12 • Handles data transfer between peripherals and memories • Eleven channels – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface – ...
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... Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. The AT91SAM7S256 features one bank of 256 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset and before the Remap Command ...
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... Security Bit Feature AT91SAM7S256 Summary Preliminary 14 The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144 bytes are organized in 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector ...
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... The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high. The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. ...
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... RCOSC XIN OSC XOUT PLL PLLRC periph_nreset usb_suspend periph_nreset periph_clk[2] dbgu_rxd PA0-PA31 AT91SAM7S256 Summary Preliminary 16 The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. System Controller Advanced fiq Interrupt Controller int MCK dbgu_irq Debug ...
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... FF00 0xFFFF FFFF 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 6 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space ...
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... NRST pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. The AT91SAM7S256 embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brown- outs occur on the VDDCORE power supply ...
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... Clock Generator 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • ...
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... Power Management Controller Advanced Interrupt Controller AT91SAM7S256 Summary Preliminary 20 The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • ...
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... Debug Unit Periodic Interval Timer Watchdog Timer Real-time Timer PIO Controller 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary • Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt vector • ...
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... Voltage Regulator Controller AT91SAM7S256 Summary Preliminary 22 – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write The aim of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 6117AS– ...
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... Peripherals Peripheral Mapping 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary Each peripheral is allocated 16 Kbytes of address space. Figure 9. User Peripheral Mapping 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 Reserved 0xFFFA FFFF 0xFFFB 0000 UDP 0xFFFB 3FFF ...
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... Peripheral Multiplexing on PIO Lines AT91SAM7S256 Summary Preliminary 24 The AT91SAM7S256 features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 32 lines. Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... SCK1 PA24 RTS1 PA25 CTS1 PA26 DCD1 PA27 DTR1 PA28 DSR1 PA29 RI1 PA30 IRQ1 PA31 NPCS1 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary Peripheral B Comments TIOA0 High-Drive TIOB0 High-Drive SCK0 High-Drive NPCS3 High-Drive TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 ...
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... AT91SAM7S256 Summary Preliminary 26 The AT91SAM7S256 embeds a wide range of peripherals. Table 4 defines the Periph- eral Identifiers of the AT91SAM7S256. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. ...
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... Two-wire Interface USART Serial Synchronous Controller Timer Counter 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary – Selectable mode fault detection – Maximum frequency Master Clock • Master Mode only • Compatibility with standard two-wire serial memories • One, two or three bytes for slave address • ...
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... PWM Controller USB Device Port Analog-to-digital Converter AT91SAM7S256 Summary Preliminary 28 – Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs, as defined in Table 5 Table 5 ...
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... AT91SAM7S256 Summary Preliminary • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • ...
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... Ordering Information Table 6. Ordering Information Ordering Code AT91SAM7S256-AI AT91SAM7S256 Summary Preliminary 30 Package LQFP 64 Temperature Operating Range Industrial (-40°C to 85°C) 6117AS–ATARM–20-Oct-04 ...
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... Document Details Title Literature Number Revision History Version A 6117AS–ATARM–20-Oct-04 AT91SAM7S256 Summary Preliminary AT91SAM7S256 6117S Publication Date: 20-Oct-04 31 ...
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... Atmel Corporation 2004. All rights reserved. Atmel ™ Everywhere You Are is the trademark of Atmel Corporation or its subsidiaries. ARM tered trademarks of ARM, Ltd. Other terms and product names may be the trademarks of others. Atmel Operations Memory ...