AT91SAM7X512 ATMEL Corporation, AT91SAM7X512 Datasheet
AT91SAM7X512
Available stocks
Related parts for AT91SAM7X512
AT91SAM7X512 Summary of contents
Page 1
... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) – ...
Page 2
... VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector • Fully Static Operation MHz at 1.65V and 85°C Worst Case Conditions • Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages AT91SAM7X512/256/128 Preliminary Summary 2 ® Infrared Modulation/Demodulation 6120DS–ATARM–03-Oct-06 ...
Page 3
... AT91SAM7X512/256/128 Preliminary Summary 1. Description Atmel's AT91SAM7X512/256/128 is a member of a series of highly integrated Flash microcon- trollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components ...
Page 4
... AT91SAM7X512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF AT91SAM7X512/256/128 Preliminary Summary 4 AT91SAM7X512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System Controller TST ...
Page 5
... AT91SAM7X512/256/128 Preliminary Summary 3. Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND ...
Page 6
... SPIx_MOSI Master Out Slave In SPIx_SPCK SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select TWD Two-wire Serial Data TWCK Two-wire Serial Clock AT91SAM7X512/256/128 Preliminary Summary 6 Active Type USB Device Port Analog Analog USART I/O I/O Input Output Input ...
Page 7
... AT91SAM7X512/256/128 Preliminary Summary Table 3-1. Signal Description List (Continued) Signal Name Function AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read ...
Page 8
... Package The AT91SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS- compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section. Figure 4-1. AT91SAM7X512/256/128 Preliminary Summary 8 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip- 100-lead LQFP Package Outline (Top View) ...
Page 9
... AT91SAM7X512/256/128 Preliminary Summary 4.2 100-lead LQFP Pinout Table 4-1. Pinout in 100-lead LQFP Package 1 ADVREF 26 2 GND 27 3 AD4 28 4 AD5 29 5 AD6 30 6 AD7 31 7 VDDOUT 32 8 VDDIN 33 9 PB27/AD0 34 10 PB28/AD1 35 11 PB29/AD2 36 12 PB30/AD3 37 13 PA8/PGMM0 38 14 PA9/PGMM1 39 15 VDDCORE 40 16 ...
Page 10
... B10 PA17/PGMD5 E5 C1 PB16 E6 C2 PB4 E7 C3 PB10 E8 C4 PB3 E9 C5 PB0 E10 AT91SAM7X512/256/128 Preliminary Summary 10 shows the orientation of the 100-ball TFBGA package. A detailed mechanical 100-ball TFBGA Package Outline (Top View BALL A1 Signal Name Pin ...
Page 11
... Power Consumption The AT91SAM7X512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. ...
Page 12
... For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. shows the power schematics to be used for USB bus-powered systems. ...
Page 13
... AT91SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. ...
Page 14
... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. AT91SAM7X512/256/128 Preliminary Summary 14 6120DS–ATARM–03-Oct-06 ...
Page 15
... AT91SAM7X512/256/128 Preliminary Summary 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM high-performance 32-bit instruction set – Thumb high code density 16-bit instruction set • ...
Page 16
... Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements AT91SAM7X512/256/128 Preliminary Summary 16 wait states 6120DS–ATARM–03-Oct-06 ...
Page 17
... AT91SAM7X512/256/128 Preliminary Summary 8. Memories 8.1 AT91SAM7X512 • 512 Kbytes of dual-plane Flash Memory – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase – ...
Page 18
... Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7X512/256/128 Preliminary Summary 18 Internal Memory Mapping 0x0000 0000 Boot Memory (1) Flash before Remap 1 MBytes SRAM after Remap 0x000F FFF 0x0010 0000 1 MBytes ...
Page 19
... After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The AT91SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program. 8.4.3 Internal Flash • ...
Page 20
... Embedded Flash 8.5.1 Flash Overview • The Flash of the AT91SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. ...
Page 21
... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.4 Security Bit Feature The AT91SAM7X512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast 6120DS–ATARM–03-Oct-06 ...
Page 22
... Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. • Communication via the DBGU supports a wide range of crystals from MHz via software auto-detection. AT91SAM7X512/256/128 Preliminary Summary 22 6120DS–ATARM–03-Oct-06 ...
Page 23
... AT91SAM7X512/256/128 Preliminary Summary • Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0. ...
Page 24
... Figure 9-1 on page 25 Figure 8-1 on page 18 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. AT91SAM7X512/256/128 Preliminary Summary 24 shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- 6120DS–ATARM–03-Oct-06 ...
Page 25
... AT91SAM7X512/256/128 Preliminary Summary Figure 9-1. NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 6120DS–ATARM–03-Oct-06 System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug ...
Page 26
... Brownout Detector and Power-on Reset The AT91SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. ...
Page 27
... AT91SAM7X512/256/128 Preliminary Summary 9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • ...
Page 28
... Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive external • 8-level Priority Controller – Drives the normal interrupt nIRQ of the processor – Handles priority of the interrupt sources AT91SAM7X512/256/128 Preliminary Summary 28 Power Management Controller Block Diagram Master Clock Controller SLCK ...
Page 29
... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x275C 0A40 (VERSION 0) for AT91SAM7X512 – Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256 – Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128 9 ...
Page 30
... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). AT91SAM7X512/256/128 Preliminary Summary 30 6120DS–ATARM–03-Oct-06 ...
Page 31
... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 Peripheral Identifiers The AT91SAM7X512/256/128 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM7X512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID 0 ...
Page 32
... Peripheral Multiplexing on PIO Lines The AT91SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
Page 33
... AT91SAM7X512/256/128 Preliminary Summary 10.4 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 RXD0 PA1 TXD0 PA2 SCK0 PA3 RTS0 PA4 CTS0 PA5 RXD1 PA6 TXD1 PA7 SCK1 PA8 RTS1 PA9 CTS1 PA10 TWD PA11 TWCK PA12 SPI_NPCS0 PA13 ...
Page 34
... PB21 PWM2 PB22 PWM3 PB23 TIOA0 PB24 TIOB0 PB25 TIOA1 PB26 TIOB1 PB27 TIOA2 PB28 TIOB2 PB29 PCK1 PB30 PCK2 AT91SAM7X512/256/128 Preliminary Summary 34 Peripheral B Comments PCK0 SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 ...
Page 35
... AT91SAM7X512/256/128 Preliminary Summary 10.6 Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • Interrupt generation to signal receive and transmit completion • ...
Page 36
... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.11 Timer Counter • Three 16-bit Timer Counter Channels – Three output compare or two input capture • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation AT91SAM7X512/256/128 Preliminary Summary 36 6120DS–ATARM–03-Oct-06 ...
Page 37
... AT91SAM7X512/256/128 Preliminary Summary – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 10-4. TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 – Two multi-purpose input/output signals – ...
Page 38
... Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Four of eight analog inputs shared with digital signals AT91SAM7X512/256/128 Preliminary Summary 38 enabled channels 6120DS–ATARM–03-Oct-06 ...
Page 39
... AT91SAM7X512/256/128 Preliminary Summary 11. Package Drawings Figure 11-1. LQFP Package Drawing 6120DS–ATARM–03-Oct-06 39 ...
Page 40
... Table 11-1. Symbol θ1 θ2 θ aaa bbb ccc ddd AT91SAM7X512/256/128 Preliminary Summary 40 100-lead LQFP Package Dimensions Millimeter Min Nom Max 1.60 0.05 0.15 1.35 1.40 1.45 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.08 0.20 0.08 0° 3.5° 7° 0° 11° 12° 13° 11° ...
Page 41
... AT91SAM7X512/256/128 Preliminary Summary Figure 11-2. 100-TFBGA Package Drawing All dimensions are in mm 6120DS–ATARM–03-Oct-06 41 ...
Page 42
... Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7X512-AU AT91SAM7X512-CU AT91SAM7X256-AU AT91SAM7X256-CU AT91SAM7X128-AU AT91SAM7X128-CU AT91SAM7X512/256/128 Preliminary Summary 42 Package Package Type LQFP 100 Green TFBGA 100 LQFP 100 Green TFBGA 100 LQFP 100 Green TFBGA 100 Temperature Operating Range Industrial (-40°C to 85°C) Industrial (-40° ...
Page 43
... Update to product functionalities including changes to Section 9.5 ”Debug Unit” on page 29 Updated PLL output range max value in 6120CS Updated information in Updated ordering information in Added AT91SAM7X512 to product Reformatted Memories Reordered sub sections in Peripherals 6120DS Consolidated Memory Mapping in Added TFBGA information added LQFP and TFBGA package drawings System Controller block diagram “ ...
Page 44
... Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel ™ istered trademarks SAM-BA and others are trademarks of Atmel Corporation or its subsidiaries. ARM are registered trademarks or trademarks of ARM Limited. Other terms and product names may be the trademarks of others. Atmel Operations Memory ...