MT29F8G08FABWP Micron Technology, Inc, MT29F8G08FABWP Datasheet - Page 16

• Manufacturer Part Number: MT29F8G08FABWP
• Manufacturer: Micron Technology, Inc

Bus Operation
Control Signals
Commands
Address Input
09005aef818a56a7 pdf/ 09005aef81590bdd source
2gb_nand_m29b__2.fm - Rev. H 9/05 EN
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins. I/O pins I/O[15:8] are used only for data in the x16 configura-
tion. Addresses and commands are always supplied on I/O[7:0].
The command sequence normally consists of a command latch cycle, an ADDRESS
LATCH cycle, and a DATA cycle—either READ or WRITE.
CE#, WE#, RE#, CLE, ALE and WP# control Flash device READ and WRITE operations.
On the 8Gb MT29F8G08FAB, CE# and CE2# each control independent 4Gb arrays. CE2#
functions the same as CE# for its own array; all operations described for CE# also apply
to CE2#.
CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the Flash memory will accept command, data, and address information.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption. See Figure 39 on page 48 and Figure 46 on page 53 for examples of CE# “Don’t
Care” operations.
The CE# “Don’t Care” operation allows the NAND Flash to reside on the same asynchro-
nous memory bus as other Flash or SRAM devices. Other devices on the memory bus
can then be accessed while the NAND Flash is busy with internal operations. This capa-
bility is important for designs that require multiple NAND devices on the same bus. One
device can be programmed while another is being read.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an address input cycle is occurring.
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are LOW, and
• CLE is HIGH, and
• the device is not busy.
The exceptions to this are the READ STATUS and RESET commands. Commands are
transferred to the command register on the rising edge of WE#. See Figure 33 on page 45.
Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must
be written with zeros when issuing a command.
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are low, and
• ALE is high, and
• the device is not busy.
Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be
written with zeros when issuing an address.
Generally all five ADDRESS cycles are written to the device. An exception to this is the
BLOCK ERASE command, which requires only three ADDRESS cycles. See the “BLOCK
ERASE Operation” section on page 35 for details.
2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Bus Operation