MT29F8G08FABWP Micron Technology, Inc, MT29F8G08FABWP Datasheet - Page 35

• Manufacturer Part Number: MT29F8G08FABWP
• Manufacturer: Micron Technology, Inc

BLOCK ERASE Operation
BLOCK ERASE 60h–D0h
Figure 27:
09005aef818a56a7 pdf/ 09005aef81590bdd source
2gb_nand_m29b__2.fm - Rev. H 9/05 EN
WE#
R/B#
ALE
I/Ox
CE#
RE#
CLE
60h
BLOCK ERASE Operation
Address Input (3 Cycles)
Erasing occurs at the block level. For example, the MT29F2G08xxB device has 2,048
erase blocks organized as 64 2,112-byte (2,048 + 64 bytes) pages per block. Each block is
132K bytes (128K + 4K bytes). The BLOCK ERASE command operates on one block at a
time. (See Figure 27.)
Three cycles of addresses A[28:18] are required for the x8 device, and three cycles of
addresses [27:17] are required for the x16 device. Although addresses A[17:12] (x8) and
A[16:11] (x16) are loaded, they are a “Don’t Care” and are ignored for BLOCK ERASE
operations. (See Figures 5 and 6 on page 11 for addressing details.)
The actual command sequence is a two-step process. The ERASE SETUP (60h) com-
mand is first written to the command register. Then three cycles of addresses are written
to the device. Next, the ERASE CONFIRM (D0h) command is written to the command
register. At the rising edge of WE#, R/B# goes LOW and the internal write state machine
automatically controls the timing and erase-verify operations. R/B# stays LOW for the
entire
The READ STATUS REGISTER command can be used to check the status of the ERASE
operation. When bit 6 = “1” the erase operation is complete. Bit 0 indicates a pass/fail
condition where “0” = pass. (See 35, and Table 9 on page 30.)
t
BERS erase time.
2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory
D0h
35
t
BERS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
70h
I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error
Command Definitions
Status
©2004 Micron Technology, Inc. All rights reserved.
Don‘t Care