MT8930CE Zarlink Semiconductor, MT8930CE Datasheet

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MT8930CE

Manufacturer Part Number
MT8930CE
Description
Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
Manufacturer
Zarlink Semiconductor
Datasheet

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MT8930CE
Manufacturer:
CML
Quantity:
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MT8930CE
Manufacturer:
MITSUBISHI
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20 000
Features
Applications
STAR/Rsto
ETS 300-012, CCITT I.430 and ANSI T1.605
S/T interface
Full-duplex 2B+D, 192 kbit/s transmission
Link activation/deactivation
D-channel access contention resolution
Point-to-point, point-to-multipoint and star
configurations
Master (NT)/Slave (TE) modes of operation
Exceeds loop length requirements
Complete loopback testing capabilities
On chip HDLC D-channel protocoller
8 bit Motorola/Intel microprocessor interface
Controllerless or microprocessor-controlled
operation
Zarlink ST-BUS interface
Low power CMOS technology
Single 5 volt power supply
ISDN NT1
ISDN S or T interface
ISDN Terminal Adaptor (TA)
Digital sets (TE1) - 4 wire ISDN interface
Digital PABXs, Digital Line Cards (NT2)
Cmode
CK/NT
DSTo
DSTi
F0od
C4b
F0b
Rsti
Interface
ST-BUS
Control
Timing
and
HALF
Figure 1 - Functional Block Diagram
AD0-7
PLL
R/W/WR,
AFT/PRI
D-channel Priority
Mechanism
CMOS ST-BUS
Microprocessor Interface
Subscriber Network Interface Circuit
Description
The MT8930C Subscriber Network Interface Circuit
(SNIC) implements the ETSI ETS 300-012, CCITT
I.430 and ANSI T1.605 Recommendations for the
ISDN S and T reference points. Providing point-to-
point and point-to-multipoint digital transmission, the
SNIC may be used at either end of the subscriber
line (NT or TE).
An HDLC D-channel protocoller is included and
controlled through a Motorola/Intel microprocessor
port.
operate without a microprocessor.
The MT8930C is fabricated in Zarlink’s CMOS
process.
DS/RD,
DinB
Transceiver
HDLC
A controllerless mode allows the SNIC to
MT8930CE
MT8930CP
AS/ALE,
P/SC
Ordering Information
-40°C to +85°C
FAMILY
28 Pin Plastic DIP
44 Pin PLCC
DReq
CS,
ISSUE 3
Activation
Controller
Interface
S-Bus
Link
Link
IRQ/NDA,
DCack
MT8930C
Data Sheet
November 1997
LTx
VBias
LRx
V
V
DD
SS
1

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MT8930CE Summary of contents

Page 1

... Control CK/NT Cmode Rsti HALF CMOS ST-BUS Subscriber Network Interface Circuit MT8930CE MT8930CP Description The MT8930C Subscriber Network Interface Circuit (SNIC) implements the ETSI ETS 300-012, CCITT I.430 and ANSI T1.605 Recommendations for the ISDN S and T reference points. Providing point-to- point and point-to-multipoint digital transmission, the SNIC may be used at either end of the subscriber line (NT or TE) ...

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MT8930C 28 1 HALF 2 27 C4b 26 F0b 3 25 F0od DSTi 23 DSTo 6 22 Cmode 7 CK/ R/W/WR, AFT/PRI DS/RD, DinB 10 18 AS/ALE, P/SC 11 CS, DReq 17 ...

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Data Sheet Pin Description (continued) Pin # Name DIP PLCC 9 16 R/W WR Read/Write or Write Input (Cmode = 1): defines the data bus transfer as a read ( write (R/W=0) in Motorola bus mode. ...

Page 4

MT8930C Pin Description (continued) Pin # Name DIP PLCC 17 26 SYNC/BA Synchronization/Bus Activity Output (Cmode = 0): output indicating synchronization to incoming RX frames when activation request is asserted and the deactivation request is ’0’ ( and ...

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Data Sheet Functional Description The MT8930C Subscriber Network Interface Circuit (SNIC multifunction transceiver providing a complete interface to the S/T Reference Point as specified in ETS 300-012, CCITT Recommendation I.430 and ANSI T1.605. Implementing point-to-point and point-to-multipoint transmission, ...

Page 6

Figure 4 - ST-BUS Channel Assignment 6 Intel microprocessor bus signals and timing. SNIC also has provisions for a controllerless mode (Cmode=0), where the microprocessor port is redefined to allow access to the control/status registers via external hardware. The three ...

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Data Sheet 7 ...

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Line Code The line code used on the S-interface is a Pseudo ternary code with 100% pulse width as seen in Figure 6 below. Binary zeros are represented as marks on the line and successive marks will alternate in polarity. ...

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Data Sheet carry data, the bit ordering must be reversed to comply with the existing datacom standards (i.e., least significant bit first). These contradicting standards place a restriction on all information input and output through the serial and parallel ports. ...

Page 10

MT8930C Signals from Info0 No Signal Info2 Valid frame structure with all B, D, D-echo and A bits set to ‘0’ Info4 Valid frame with data D-echo channels. Bit A is set to 1. ...

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Data Sheet operating in adaptive timing TR is the line termination resistor = 100 Ω operating in fixed timing TR is the line termination resistor = 100 Ω Fiure 9 ...

Page 12

MT8930C Channel Channel 0 1 Bit 7 F0b C4b ST-BUS Channel 31 BIT CELLS Bit 0 Figure 12 - Clock & Frame Alignment for ST-BUS Streams ST-BUS Interface The ST-BUS is a synchronous time division multiplexed serial bussing scheme with ...

Page 13

Data Sheet ST-BUS Clock ST-BUS Stream MT8930C NT System F0b Frame Pulse F0od to TE System to TE Frame Pulse Input ST-BUS Stream eight SNICs in NT mode with physically independent S-Busses can be connected in ...

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MT8930C Address Lines ...

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Data Sheet Diagnostic Register cleared. Once full activation is achieved the Diagnostic Register can be written to in order to enable the various test functions. HDLC Transceiver The HDLC Transceiver handles the bit oriented protocol structure and formats the D-channel ...

Page 16

Interframe Time Fill When the HDLC Tranceiver is not sending packets, the transmitter can be in one of two states mentioned below depending on the status of the IFTF bit in the HDLC Control Register 1. i) Idle State The ...

Page 17

Data Sheet must be set HIGH, before writing the next byte into the FIFO. This bit is cleared automatically once the byte is written to the Transmit FIFO. ‘flagged’ byte reaches the bottom of the FIFO, a frame abort sequence ...

Page 18

Byte” status on any of its bytes. iv) Idle Channel While receiving the idle channel, the idle bit in the HDLC status register remains set. v) Transparent Data Transfer By setting ...

Page 19

Data Sheet BIT NAME (3) B7 CH3i If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel). If ’0’, then the channel is disabled, and will read FF (3) B6 CH2i If ’1’, then the ST-BUS channel 2 ...

Page 20

MT8930C BIT NAME B7-B5 NA Keep at ’0’ for normal operation. B4 Trans A ’1’ will place the HDLC in a transparent mode. This will perform the serial to parallel or parallel to serial conversion without inserting or deleting the ...

Page 21

Data Sheet BIT NAME B7 EnDcoll A ’1’ will enable the D-channel collision interrupt. A ’0’ will disable it. This bit is available only in TE mode. B6 EnEOPD A ’1’ will enable the received End of Packet interrupt. A ...

Page 22

MT8930C BIT NAME B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB). If address recognition is enabled, any packet failing the address comparison will not be stored in the ...

Page 23

Data Sheet BIT NAME B7-B6 Loop The status of these two bits determine which type of loopback performed: B5 FSync If ’1’, the device will maintain frame synchronization even after losing the framing sequence (i.e., if the ...

Page 24

MT8930C BIT NAME B7 AR Setting this bit will initiate the activation of the S-Bus. If ’0’, the device will remain in the present state Setting this bit will initiate the deactivation of the S-Bus. If ’0’, the ...

Page 25

Data Sheet BIT NAME B7 Sync/BA This bit is set if the device has achieved frame synchronization while the activation request is asserted ( and AR = 1). If there is a deactivation request or that AR is ...

Page 26

Applications The MT8930C is useful in a wide variety of ISDN applications. Being used at both the Network Termination (NT) and Terminal Equipment (TE) ends of the line, the SNIC finds application on digital subscriber line cards and in full ...

Page 27

Data Sheet Termination Network MH89101 U Reference Point Figure 17 - NT1 using the MT8910-1 (DSLIC) and MT8930C (SNIC) MT8930C ‡ R LTx V Bias ‡ R LRx 1:2 2kΩ IRQ + ...

Page 28

MT8930C MT8930C AD0-AD7 Connections to interface to MC6809 Figure 19 - Interfacing to the MC6802 Microprocessor ETS 300-012 NT&TE Line Interface Figures 20, 21 and 22 show the recommended line interface circuits for meeting the ETS 300-012 requirements. These circuits ...

Page 29

Data Sheet In Figure 21, two types of diodes (germanium 1N270 or schottky MBD301) can be used for D5,6. 1N270 will leave more margin for pulse template and longitudinal conversion loss. However, MBD301 will leave more margin for impedance template. ...

Page 30

MT8930C MT8930C D5 LTx Bias R1 LRx Figure 21 - ETS 300-012 NT & TE Line Interface for VAC X027 or X028 ...

Page 31

Data Sheet MT8930C R1 LTx Bias R2 LRx V SS Figure 23 - Proprietary NT & TE Line Interface ...

Page 32

MT8930C Absolute Maximum Ratings Parameters 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions ...

Page 33

Data Sheet AC Electrical Characteristics Characteristics 1 F0b input pulse width 2 Frame pulse (F0b) set-up time 3 Frame pulse (F0b) hold time 4 C4b input clock period 5 C4b pulse width High or Low 6 C4b transition time 7 ...

Page 34

MT8930C AC Electrical Characteristics Characteristics 1 F0b output pulse width 2 C4b to (F0b) delay 3 C4b to (F0b) hold time 4 C4b output clock period 5 C4b pulse width High or Low 6 C4b transition time 7 F0od delay ...

Page 35

Data Sheet AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address Latch pulse width 4 Address setup time 5 Address hold time 6 Data setup time - Write 7 Data hold time - ...

Page 36

MT8930C AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address strobe pulse width 4 Data strobe setup time 5 Data strobe hold 6 Data strobe pulse width 7 Read/Write setup time 8 Read/Write ...

Page 37

Data Sheet AC Electrical Characteristics Characteristics 1 C inputs setup time (TE Mode) mode 2 C inputs setup time (NT Mode) mode 3 C inputs hold time (TE Mode) mode 4 C inputs hold time (NT Mode) mode 5 C ...

Page 38

MT8930C Notes: 38 Data Sheet ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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