74ABT16646CMTD Fairchild Semiconductor, 74ABT16646CMTD Datasheet

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74ABT16646CMTD

Manufacturer Part Number
74ABT16646CMTD
Description
IC TRANSCVR TRI-ST 16BIT 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet
1.74ABT16646CMTD.pdf (9 pages)

Specifications of 74ABT16646CMTD

Logic Type
Transceiver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 1999 Fairchild Semiconductor Corporation
74ABT16646CSSC
74ABT16646CMTD
74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
A
B
CPAB
SAB
OE
DIR
0
0
Pin Names
–A
–B
n
n
15
15
, SBA
n
, CPBA
n
Package Number
n
MS56A
MTD56
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS011644
Features
Connection Diagram
Independent registers for A and B buses
Multiplexed real-time and stored data
A and B output sink capability of 64 mA, source
capability of 32 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Package Description
October 1993
Revised November 1999
www.fairchildsemi.com

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74ABT16646CMTD Summary of contents

Page 1

... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Function Table Inputs OE DIR CPAB CPBA SAB ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...

Page 5

DC Electrical Characteristics (SSOP Package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...

Page 6

Extended AC Electrical Characteristics (SSOP Package) Symbol Parameter t Propagation Delay PLH t Clock to Bus PHL t Propagation Delay PLH t Bus to Bus PHL t Progagation Delay PLH t SBA or SAB PHL n ...

Page 7

Skew (SOIC Package) Symbol Parameter t Pin to Pin Skew OSHL (Note 15) HL Transitions t Pin to Pin Skew OSLH (Note 15) LH Transitions t Duty Cycle PS (Note 16) LH–HL Skew t Pin to Pin Skew OST (Note ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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