AD1853 Analog Devices, AD1853 Datasheet
AD1853
Available stocks
Related parts for AD1853
AD1853 Summary of contents
Page 1
... DSP serial port compatible modes. The AD1853 accepts serial audio data in MSB first, twos complement format. The AD1853 operates from a single +5 V power supply fabricated on a single monolithic integrated circuit and is housed in a 28-lead SSOP package for operation over the temperature range 0° ...
Page 2
... AD1853–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages ( +5 Ambient Temperature +25°C 24.576 MHz (512 × F Input Clock Input Signal 996.094 kHz –0.5 dB Full Scale Input Sample Rate 48 kHz Measurement Bandwidth kHz Word Width 20 Bits Input Voltage HI 3 ...
Page 3
... Group Delay 903.8 911.6 921 10%) Min 54 0.4 × t DMP 0.4 × t DMP 20 20 140 AD1853 Units Units °C °C °C Units µs µs µs Units ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1853 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... LR Clock Cycles. Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is reset on the rising edge of this signal. The serial control port registers are reset to the default values ...
Page 6
... AD1853 L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA LSB MSB INPUT L/RCLK INPUT BCLK INPUT SDATA MSB MSB–1 MSB–2 INPUT L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA MSB MSB–1 MSB–2 LSB+2 INPUT L/RCLK LEFT CHANNEL INPUT BCLK ...
Page 7
... OPERATING FEATURES Serial Data Input Port The AD1853’s flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The serial mode is set by using either the external mode pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI control register ...
Page 8
... AD1853 applications without requiring the use of the serial control port. For those users that do not use the serial control port still possible to mute the AD1853 output by using the MUTE pin (Pin 23) signal. Note that the serial control port timing is asynchronous to the serial data port timing ...
Page 9
... It is organized around three registers; a LEFT-CHANNEL VOLUME register, a RIGHT-CHANNEL VOLUME register and a CONTROL register. Each WRITE operation to the AD1853 SPI control port requires 16 bits of serial data in MSB-first format. The bottom two bits are used to select one of three registers, and the top 14 bits are then written to that register ...
Page 10
... If possible, the AD1853 should be placed in mute before such a change is made. plots is higher than the actual noise floor of the AD1853. This is caused by the higher noise floor of the “High Bandwidth” ADC used in the Audio Precision measurement system. The two-tone test shown in Figure 18 is per the SMPTE standard for measur- ing Intermodulation Distortion ...
Page 11
... Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz kHz, 24-Bit –11– AD1853 0 50 100 150 200 250 FREQUENCY – kHz 0 50 100 150 200 FREQUENCY – kHz –100 –80 – ...
Page 12
... AD1853 2 0 –2 –4 –6 –8 –10 –12 10 100 1k FREQUENCY – Hz Figure 17. Normal De-Emphasis Frequency Response Input @ –10 dBFS kHz –10 –30 –50 –70 –90 –110 –130 –150 FREQUENCY – kHz Figure 18. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS 0 –20 – ...
Page 13
... Figure 27. Wideband Plot, 75 kHz Input, 2 × Interpolation, SR 192 kHz 80 100 120 –13– AD1853 FREQUENCY – kHz FREQUENCY – kHz ...
Page 14
... Cd/F1 DVDD Ce/F2 SEL CSI2/FCK DGND DGND DEEMPH MUTE HDR1 DVDD 1 CDATA CCLK CLATCH I/F MCLK 10k 10k 10k Figure 28. Digital Receiver, MUX and AD1853 DAC –14– HDR3 44/ DVDD R18 192 0 1 10k DVDD IDPM1 S2C ...
Page 15
... J8 –15V dc FB5 CR3 J4 600Z 1N4001 + +15V dc + C27 10 F – CR1 1SMB15AT3 J5 0V DGND Figure 29. DAC Output LP Filter, Power and Reset –15– AD1853 C38 220pF NP0 R41 J2 604 1 RIGHT U8B OUT 0 C50 R43 2.2nF OP275 49.9k NP0 C39 220pF NP0 GAUSSIAN FILTER RESPONSE – ...
Page 16
... AD1853 68pF, NP0 PIN 12 LOUT+ PIN 13 LOUT– PIN 17 ROUT+ PIN 16 ROUT– 68pF, NP0 V REF +2.78V C15 + 100nF – TANT NOTE: = AGND 0.311 (7.9) 0.301 (7.64) 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) I/V CONVERTERS AND LP FILTER R9* 2.87k GAUSSIAN FILTER RESPONSE –3dB CORNER FREQUENCY: 75kHz ...