MT29F8G08FACWP Micron Technology, MT29F8G08FACWP Datasheet - Page 15

• Manufacturer Part Number: MT29F8G08FACWP
• Description: NAND Flash Memory
• Manufacturer: Micron Technology

Figure 9:
Table 6:
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
Cycle
First
Second
Third
Fourth
Fifth
www.DataSheet4U.net
Cache Register
Data Register
4,096 blocks
per device
Array Addressing for MT29F4G08BxC and MT29F8G08FxC (x8)
Array Organization for MT29F4G08BxC and MT29F8G08FxC (x8)
BA15
LOW
LOW
I/O7
CA7
BA7
Notes: 1. If CA11 = “1” then CA[10:6] must be “0.”
Note:
2. Die address boundary: “0” = 0Gb–2Gb devices, “1” = 2Gb–4Gb devices.
3. Block address concatenated with page address = actual page address. CAx = column
BA14
LOW
LOW
I/O6
CA6
BA6
For the 8Gb MT29F8G08F, the 4Gb array organization shown here applies to each chip
enable (CE# and CE2#).
address; PAx = page address, BAx = block address.
2,048
2,048
1 Block
BA13
LOW
LOW
I/O5
CA5
PA5
2,112 bytes
BA12
LOW
LOW
I/O4
CA4
PA4
15
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory
64
64
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CA11
BA11
LOW
I/O3
CA3
PA3
64 pages = 1 block
1 page
1 block
1 device = (2K + 64) bytes x 64 pages
1
I/O 7
I/O 0
CA10
BA10
LOW
= (2K + 64) bytes
= (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
= 4,224Mb
I/O2
CA2
PA2
x 4,096 blocks
(128K + 4K) bytes
©2005 Micron Technology, Inc. All rights reserved.
Memory Mapping
BA17
I/O1
CA1
CA9
BA9
PA1
2
BA16
I/O0
CA0
CA8
BA8
PA0