MT29F8G08FACWP Micron Technology, MT29F8G08FACWP Datasheet - Page 24

• Manufacturer Part Number: MT29F8G08FACWP
• Description: NAND Flash Memory
• Manufacturer: Micron Technology

RANDOM DATA READ 05h-E0h
Figure 18:
PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh
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2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
R/B#
I/Ox
RE#
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00h
RANDOM DATA READ Operation
(5 Cycles)
Address
30h
The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h-30h) sequence.
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (two cycles).
The RANDOM DATA READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially
(see Figure 18).
Micron NAND Flash devices have a cache register that can be used to increase the READ
operation speed when accessing sequential pages in a block.
First, a normal PAGE READ (00h-30h) command sequence is issued. See Figure 19 on
page 25 for operation details. The R/B# signal goes LOW for
transfer the first page of data from the memory to the data register. After R/B# returns to
HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the com-
mand register. R/B# goes LOW for
data register to the cache register. Once the data register contents are transferred to the
cache register, another PAGE READ is automatically started as part of the 31h command.
Data is transferred from the next sequential page of the memory array to the data regis-
ter during the same time data is being read serially (pulsing of RE#) from the cache regis-
ter. If the total time to output data exceeds
The second and subsequent pages of data are transferred to the cache register by issuing
additional 31h commands. R/B# will stay LOW up to
depending on whether the previous memory-to-data-register transfer was completed
prior to issuing the next 31h command. See Table 21 on page 45 for timing parameters.
If the data transfer from memory to the data register is not completed before the 31h
command is issued, R/B# stays LOW until the transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h command.
R/B# will stay LOW until the previous PAGE READ is complete and the data has been
transferred to the cache register.
To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh)
command is issued. This command transfers data from the data register to the cache
register without issuing another PAGE READ (see Figure 19 on page 25).
t R
Data Output
24
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory
t
DCBSYR1 while data is being transferred from the
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05h
t
R, then the PAGE READ is hidden.
(2 Cycles)
Address
t
DCBSYR2. This time can vary,
E0h
Command Definitions
t
R during the time it takes to
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Data Output