MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet

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MT9M019

Manufacturer Part Number
MT9M019
Description
1/5-Inch 1.3Mp CMOS Digital Image Sensor
Manufacturer
Aptina Imaging Corporation
Datasheet
1/5-Inch 1.3Mp CMOS Digital Image Sensor
MT9M019 Data Sheet
For the latest MT9M019 data sheet, refer to Aptina’s Web site at
Features
• DigitalClarity
• Low dark current
• Simple two-wire serial interface
• Auto black level calibration
• Support for external LED or xenon flash
• High frame rate preview mode with arbitrary down-
• Programmable controls: gain, frame size/rate,
• SMIA-compatible
• Data interface: CCP2-compliant sub-low-voltage
• On-chip phase-locked loop (PLL) oscillator
• Bayer pattern downsize scaler
• Superior low-light performance
Applications
• Cellular phones
• Digital still cameras
• PC cameras
• PDAs
General Description
The Aptina
CMOS active-pixel digital image sensor with a pixel
array of 1280H x 1024V (1288H x 1032V including bor-
der pixels). It incorporates sophisticated on-chip cam-
era functions such as windowing, mirroring, column
and row skip modes, and snapshot mode. It is pro-
grammable through a simple two-wire serial interface
and has very low power consumption.
The MT9M019 digital image sensor features Digital-
Clarity—Aptina’s breakthrough low-noise CMOS imag-
ing technology that achieves near-CCD image quality
(based on signal-to-noise ratio and low-light sensitiv-
ity) while maintaining the inherent size, cost, and inte-
gration advantages of CMOS.
PDF: 7723845879/Source:2828556980
MT9M019_DS - Rev. F 5/10 EN
size scaling from maximum resolution
exposure, left–right and top–bottom image reversal,
window size, and panning
differential signalling (sub-LVDS)
®
MT9M019 is a 1/5-inch SXGA-format
®
CMOS imaging technology
Products and specifications discussed herein are subject to change by Aptina without notice.
1
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
www.aptina.com
Table 1:
When operated in its default mode, the sensor gener-
ates a SXGA image at 30 frames per second (fps). An
on-chip analog-to-digital converter (ADC) generates a
10-bit value for each pixel.
Ordering Information
Table 2:
Optical format
Active imager size
Active pixels
Pixel size
Color filter array
Shutter type
Maximum data rate/
master clock
Frame
rate
ADC resolution
Responsivity
Dynamic range
SNR
Supply
voltage
Power consumption
Operating temperature
Packaging
Chief Ray Angle
MT9M019D00STCC14BC1
MAX
Parameter
Part Number
SXGA
(1280 x 1024)
VGA
(640 x 480)
Analog
Digital
Key Performance Parameters
Available Part Numbers
Aptina reserves the right to change products or specifications without notice.
1/5-inch SXGA (5:4)
2.83mm(H) x 2.27(V)
3.63mm diagonal
(calculated from 1288 x 1032)
1288H x 1032V
2.2 x 2.2μm
RGB Bayer pattern
Electronic rolling shutter (ERS)
64 Mp/s at 64 MHz system clock
Programmable up to 30 fps
Programmable up to 60 fps
10-bit, on-chip (61dB)
1.14V/lux-sec
67.27dB
36.4dB
2.4–3.1V (2.80V nominal)
1.7–1.9V (1.80V nominal)
190mW
–30°C to +70°C
Die
24.77° at 85% image height
©2006 Aptina Imaging Corporation All rights reserved.
Description
Value
www.DataSheet4U.com
Bare die
Features

Related parts for MT9M019

MT9M019 Summary of contents

Page 1

... CMOS Digital Image Sensor MT9M019 Data Sheet For the latest MT9M019 data sheet, refer to Aptina’s Web site at Features ® • DigitalClarity CMOS imaging technology • Low dark current • Simple two-wire serial interface • Auto black level calibration • ...

Page 2

... Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Image Acquisition Mode .29 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PDF: 7723845879/Source:2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Aptina reserves the right to change products or specifications without notice. 2 Table of Contents www.DataSheet4U.com ©2006 Aptina Imaging Corporation. All rights reserved. ...

Page 3

... Operating Voltages .49 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 SMIA Specification Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Revision History .53 PDF: 7723845879/Source:2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Aptina reserves the right to change products or specifications without notice. 3 Table of Contents www.DataSheet4U.com ©2006 Aptina Imaging Corporation. All rights reserved. ...

Page 4

... Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 9: Effect of Limiter on SMIA Data Path .16 Figure 10: Timing of SMIA Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 11: MT9M019 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 12: MT9M019 SMIA Profile 1, 2 Clocking Structure .24 Figure 13: MT9M019 SMIA Profile 0 Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 14: Pixel Readout (no subsampling .30 Figure 15: Pixel Readout (x_odd_inc = 3, y_odd_inc = .30 Figure 16: Pixel Readout (x_odd_inc = 1, y_odd_inc = 3) ...

Page 5

... SMIA Characterization Data Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 22: Electrical Characteristics (FLASH .51 Table 23: Absolute Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Aptina reserves the right to change products or specifications without notice. 5 List of Tables www.DataSheet4U.com ©2006 Aptina Imaging Corporation. All rights reserved. ...

Page 6

... Functional Overview The MT9M019 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal clocks from a single master input clock running between 6 and 27 MHz. The maximum pixel rate is 64 Mp/s, corresponding to a system clock rate of 64 MHz. A block diagram of the sensor is shown in Figure 1 ...

Page 7

... Operating Modes By default, the MT9M019 powers SMIA-compatible sensor with the serial pixel data interface enabled. A typical configuration in this mode is shown in Figure 2. Figure 2: Typical Configuration: Serial Pixel Data Interface 6–27 MHz General purpose From Controller S ADDR Notes: 1. All power supplies should be adequately decoupled. ...

Page 8

... Signal Descriptions Table 3 provides signal descriptions for MT9M019 die. For pad location and aperture information, refer to the MT9M019 die data sheet. Table 3: Signal Descriptions Pad Name Pad Type EXTCLK Input RESET_N Input (XSHUTDOWN) SCLK Input GPI[1:0] Input TEST Input S I/O DATA DATA_P ...

Page 9

... LOW—the interface protocol determines which device is allowed to drive S given time. The protocols described in the I LOW. However, the MT9M019 uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low- level protocol elements, as follows: • ...

Page 10

... The slave’s internal register address is auto-incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no- acknowledge bit. PDF: 7723845879/Source:2828556980 MT9M019 DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface . The receiver indicates an acknowl- DATA LOW. As for data transfers, S DATA Aptina reserves the right to change products or specifications without notice ...

Page 11

... A = no-acknowledge Single READ from Current Location This sequence (Figure 4) performs a read using the current value of the MT9M019 internal register address. The master terminates the READ by generating a no-acknowl- edge bit followed by a stop condition. The figure shows two independent READ sequences ...

Page 12

... The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 7: Single WRITE to Random Location S Slave Address 0 PDF: 7723845879/Source:2828556980 MT9M019 DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor A Reg Address[7: M+2 M+L-2 M+3 Read Data A ...

Page 13

... Figure 8: Sequential WRITE, Start at Random Location S Slave Address 0 A Reg Address[15:8] M+1 Write Data A PDF: 7723845879/Source:2828556980 MT9M019 DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Previous Reg Address Reg Address[7:0] A M+2 M+3 Write Data Write Data A 13 Two-Wire Serial Register Interface www.DataSheet4U.com ...

Page 14

... The SMIA specification imposes a number of programming restrictions. An implemen- tation naturally imposes additional restrictions. Table 5 shows a list of programming rules that must be adhered to for correct operation of the MT9M019 recommended that these rules are encoded into the device driver stack, either implicitly or explicitly. ...

Page 15

... Notes: 1. SMIA FS = SMIA Functional Specifications. PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Minimum Value scaler_n_min 256 (this is enforced in hardware: values lower than this are treated as 256) 0 ...

Page 16

... Effect of Scaler on Legal Range of Output Sizes When the scaler is enabled necessary to adjust the values of x_output_size and y_output_size to match the image size generated by the scaler. The MT9M019 will not operate properly if the x_output_size and y_output_size are significantly larger than the output image. To understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction) ...

Page 17

... If this has the effect of extending LINE_VALID across the whole of the horizontal blanking time, as shown Figure 9 on page 16, the MT9M019 will cease to generate output frames. A correct configuration is shown in Figure 10. This figure shows the x_output_size reduced to match the output size of the scaler ...

Page 18

... If this constraint is not met, the FIFO will either underrun or overrun. FIFO underrun or overrun is a fatal error condition that is signalled through the data path_status register (R0x306E–F). PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Programming Restrictions Aptina reserves the right to change products or specifications without notice. 18 www.DataSheet4U.com © ...

Page 19

... Profile 0/1, 2 selection PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Programming Restrictions Aptina reserves the right to change products or specifications without notice. 19 www.DataSheet4U.com ©2006 Aptina Imaging Corporation. All rights reserved. ...

Page 20

... There is no dedicated S This interface is described in detail in “Two-Wire Serial Register Interface” on page 9. Default Power-up State At power-up and after a hard or soft reset, the reset state of the MT9M019 is under SMIA operation and the CCP2 high-speed serial interface. Serial Pixel Data Interface The serial pixel data interface uses the following output-only signal pairs: • ...

Page 21

... System States The system states of the MT9M019 are represented as a state diagram in Figure 11 and described in subsequent sections. The effect of RESET_N on the system state and the configuration of the PLL in the different states are shown in Table 6. The sensor’s operation is broken down into three separate states: Hardware standby, software standby, and streaming ...

Page 22

... Power-On Reset Sequence When power is applied to the MT9M019, it enters a low-power hardware standby state. Exit from this state is controlled by the later of two events: 1. The negation of the RESET_N input timeout of the internal power-on reset circuit possible to hold RESET_N permanently negated and rely upon the internal power- on reset circuit ...

Page 23

... The gpi_status register is used to associate a function with a general purpose input. Streaming/Standby Control The MT9M019 can be switched between its soft standby and streaming states under pin or register control, as shown in Table 8. Selection of a pin to use for the STANDBY func- tion is described in “General Purpose Inputs” on page 23. The state diagram for transi- tions between soft standby and streaming states is shown in Figure 11 on page 21 ...

Page 24

... Clocking The MT9M019 contains a phase-locked loop (PLL) for timing generation and control. The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and a set of dividers to generate the output clocks. Both SMIA profile 0 clock scheme and profile 1, 2 are supported. The clocking scheme can be selected by either setting register 0x306E– ...

Page 25

... In Profile 1,2, the output clock frequencies can be calculated as: vt_pix_clk_freq_mhz = op_pix_clk_freq_mhz = PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor op_sys_clk_div ...

Page 26

... CCP2 output. PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor ext_clk_freq_mhz*pll_multiplier -------------------------------------------------------------------------------- - pre_pll_clk_div*op_sys_clk_div PLL Output Clock ...

Page 27

... PLL. The PLL is enabled by entering the streaming state. An external timer will delay entering streaming mode by 6,750 EXTCLKs so that the PLL can lock. The effect of programming the PLL divisors while the MT9M019 is in the streaming state is UNDEFINED. Influence of ccp_data_format The ccp_data_format register (R0x0112–3) controls whether the pixel data interface will generate 10 bits per pixel or 8 bits per pixel. The raw output of the sensor core is 10-bits per-pixel ...

Page 28

... EXTCLK. The register settings for this example and the resulting clock frequencies are shown in Table 11. If the MT9M019 is programmed with these values (and all other registers are left at their default values), and is then put into streaming mode (mode_select=1) it will stream frames at full resolution (1,280 x 1,024 pixels) through its CCP2 interface at 31 ...

Page 29

... MT9M019 switches cleanly from the old integration time to the new while only gener- ating frames with uniform integration. ...

Page 30

... Figures 14 through 17. Figure 14: Pixel Readout (no subsampling) Figure 15: Pixel Readout (x_odd_inc = 3, y_odd_inc = 1) PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor X incrementing X incrementing Aptina reserves the right to change products or specifications without notice. 30 Features www.DataSheet4U.com ...

Page 31

... The adjustment should be made in accordance with the following rule: remainder = (addr_end - addr_start + 1) AND 0x0002; if (remainder == 0) addr_end = addr_end - 2; PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor X incrementing X incrementing Aptina reserves the right to change products or specifications without notice. 31 Features www.DataSheet4U.com © ...

Page 32

... There are two possible subsampling sequences (because the subsampling sequence only read half of the rows and columns) depending upon the alignment of the start address. Table 12: Row Address Sequencing Frame Rate Control The formula for calculating the frame rate of the MT9M019 is shown below: ⎛ line_length_pck = ⎝ ⎛ ...

Page 33

... Valid Data Signal Options Integration Time The integration (exposure) time of the MT9M019 is controlled by the fine_integration_time and coarse_integration_time registers. The limits for the fine integration time are defined by: < = fine_integration_time_min fine_integration_time The limits for the coarse integration time are defined by: coarse_integration_time_min If coarse_integration_time> ...

Page 34

... Flash Control The MT9M019 supports both xenon and LED flash through the FLASH output signal. The timing of the FLASH signal with the default settings is shown in Figure 18, 19, and 20. The flash and flash_count registers allow the timing of the flash to be changed. The flash can be programmed to fire only once, be delayed by a few frames when asserted, and (for Xenon flash) the flash duration can be programmed ...

Page 35

... SMIA limiter registers therefore need to be reprogrammed by the host to match the new internal pixel clock frequency. PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor FRAME VALID Flash STROBE Flash enabled Masked out ...

Page 36

... Analog Gain The MT9M019 provides two mechanisms for setting the analog gain. The first uses the SMIA gain model. The second uses the traditional Aptina gain model. The following sections describe both models, the mapping between the models, and the operation of the per-color and global gain control ...

Page 37

... The result of this is that the two gain models can be used interchangeably but, having written gains through one set of registers, those gains should be read back through the same set of registers. PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Aptina reserves the right to change products or specifications without notice. 37 Features www.DataSheet4U.com ...

Page 38

... Test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). For all of the test patterns, the MT9M019 registers must be set appropriately to control the frame rate and output timing. This includes: • ...

Page 39

... The effect of subsampling and scaling of this test pattern is UNDEFINED. Figure 21: 100 Percent Color Bars Test Pattern Horizontal mirror = 0 PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Sensor Core Digital Data Path Horizontal mirror = 1 Aptina reserves the right to change products or specifications without notice. 39 www.DataSheet4U.com ...

Page 40

... Any pattern repeat occurs on the right side of the output image regardless of the setting of horizontal_mirror. The effect of subsampling and scaling of this test pattern is UNDEFINED. PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor 1024. 40 Sensor Core Digital Data Path www ...

Page 41

... Note: Figures are for illustration purposes only. PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Sensor Core Digital Data Path Horizontal mirror = 1, Vertical flip = 0 Horizontal mirror = 1, Vertical flip = 1 Aptina reserves the right to change products or specifications without notice. ...

Page 42

... The effect of enabling the test cursors when the image_orientation register is non-zero is not defined by the SMIA specification. The behavior of the MT9M019 is shown in Figure 23 on page 43, where the test cursors are shown as translucent, for clarity. In prac- tice, they are opaque (they overlay the imaged scene) ...

Page 43

... The only way to disable the effect of the pedestal is to set it to “0.” PDF: 7723845879/Source:2828556980 MT9D019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Horizontal mirror = 0, Vertical flip = 0 Vertical cursor start Horizontal mirror = 0, Vertical flip = 1 ...

Page 44

... Figure 24 shows the die outline, including the readout orientation, the optically-active area, and the offset of the optical center from the die center. Figure 24: Die Outline - PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor ...

Page 45

... CRA vs. Image Height Plot 100 PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor 450 550 650 750 Wavelength (nm) Image Height (%) 45 Spectral Characteristics www.DataSheet4U.com Blue Green (B) Green (R) ...

Page 46

... The electrical characteristics of the EXTCLK input are shown in Table 15. The EXTCLK input supports either an AC-coupled sine-wave input clock or a DC-coupled square- wave input clock. If EXTCLK is AC-coupled to the MT9M019 and the clock is stopped, the EXTCLK input to the MT9M019 must be driven to ground excessive current consumption within the EXTCLK input receiver. ...

Page 47

... Drive current variation Output impedance Output impedance mismatch Clock duty cycle @ 416 MHz Vod Rise time (20–80%) PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor signals feature fail-safe input protection, DATA CCP (V IO) = 1.8V 2.8V; VAAPIX = 2.8V Conditions No pull-up resistor ...

Page 48

... Minimum V spike width DD below V _F TRIG ALLING considered reset when POR cell output is LOW PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor CCP (V IO) = 1.8V 2.8V; VAAPIX = 2.8V Conditions CCP (V IO) = 1.8V 2.8V; VAAPIX = 2.8V Conditions No pull-up resistor ...

Page 49

... Figure 27: Internal Power-On Reset Digital Power Supply V DD POR Cell Output POR Cell Output Operating Voltages V and VAAPIX must be at the same potential for correct operation of the MT9M019. AA Table 20: DC Electrical Definitions and Characteristics f EXTCLK = 16 MHz 1.8V Ambient temperature; 0 lux on sensor ...

Page 50

... Power Supply Rejection Ratio (PSRR): Value * : in case of SMIA test method which fixed amplitude noise PSRR at 50Hz ~10 kHz PSRR at ~1 MHz PSRR at ~10 MHz Image Lag as wafer level test data PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor CCP (V IO) = 1.8V 2.8V; VAAPIX = 2.8V ...

Page 51

... Output LOW current OL I Output LOW current OL I Tri-state output leakage current OZ Ouput pin slew PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Sensor Dependency Parameters Lower Limit = 1.8V 1.8V; VAA = 2.8V; VAAPIX = 2.8V; VDDPLL = 2.8V; DD Conditions At specified I 8mA OH At specified I ...

Page 52

... Part 1: Functional Specification ECR0001 (Version 1.0 dated 11-Feb-2005) • Electrical Specification: – SMIA 1.0 Part 2: CCP2 Specification (Version 1.0 dated 30-June-2004); SMIA 1.0 Part 2: CCP2 Specification ECR0002 (Version 1.0 dated 11-Feb-2005) PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Conditions Min –0.3 –0.3 –0.3 – ...

Page 53

... Table 6, “PLL in System States,” on page 21 • Update "Power-On Reset Sequence" on page 22 • Update "General Purpose Inputs" on page 23 • Update Figure 12: “MT9M019 SMIA Profile 1, 2 Clocking Structure,” on page 24 • Add "Programming Example" on page 28 • Add Table 11, “Default Settings,” on page 28 • ...

Page 54

... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 7723845879/Source: 2828556980 MT9M019_DS - Rev. F 5/10 EN MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor Aptina reserves the right to change products or specifications without notice. 54 Revision History www.DataSheet4U.com © ...

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