MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet
MT8VDDT6464HD
Related parts for MT8VDDT6464HD
MT8VDDT6464HD Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB (x64) 200-PIN DDR SODIMM MT8VDDT1664HD – 128MB MT8VDDT3264HD – 256MB MT8VDDT6464HD – 512MB For the latest data sheet, please refer to the Micron site: www.micron.com/moduleds Figure 1: 200-Pin SODIMM (MO-224) OPTIONS • ...
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... MT8VDDT3264HDY-265__ MT8VDDT3264HDG-202__ MT8VDDT3264HDY-202__ MT8VDDT6464HDG-335__ MT8VDDT6464HDY-335__ MT8VDDT6464HDG-262__ MT8VDDT6464HDY-262__ MT8VDDT6464HDG-26A__ MT8VDDT6464HDY-26A__ MT8VDDT6464HDG-265__ MT8VDDT6464HDY-265__ MT8VDDT6464HDG-202__ MT8VDDT6464HDY-202__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264HDG-265A1. 09005aef806e1d28 DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN MODULE ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL REF DQ19 SS 5 DQ0 55 DQ24 7 DQ1 DQ25 DD ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information PIN NUMBERS 118, 119, 120 35, 37, 158, 160 95, 96 www.DataSheet4U.com 121, 122 116, 117 99 (256MB, ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information PIN NUMBERS 13, 14, 17, 18, 19, 20, 23, 20, 29, 30, 31, 32, ...
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S1# S0# CS# DQS0 UDQS DM0 UDM DQ0 DQ DQ1 DQ DQ2 DQ DQ3 DQ DQ4 DQ DQ5 DQ DQ6 DQ www.DataSheet4U.com DQ DQ7 U1 DQS1 LDQS DM1 LDM DQ8 DQ DQ9 DQ DQ10 DQ DQ11 DQ DQ12 DQ DQ13 ...
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... General Description The MT8VDDT1664HD, MT8VDDT3264HD, and MT8VDDT6464HD, are high-speed CMOS, dynamic random-access, 128MB, 256MB, and 512MB memory modules organized in x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAMs. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double ...
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A7–A12 (256MB, 512MB) specify the oper- ating mode. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition Diagram. The ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS www.DataSheet4U.com 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6 ...
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BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode regis- ter (BA0/BA1 ...
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Commands The Truth Tables below provides a general reference of available commands. For a more detailed descrip- Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) w ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 128MB Module DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 50; notes appear on pages 20–23; 0°C £ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 13: I Specifications and Conditions – 256MB Module DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 50; notes appear on pages 20–23; 0°C £ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 14: I Specifications and Conditions – 512MB Module DD DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 50; notes appear on pages 20–23; 0°C £ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 15: Capacitance Note: 11; notes appear on pages 20–23 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#, CKE Input Capacitance: CK, CK# www.DataSheet4U.com Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 12–15, 29, 50; notes appear on pages 20–23; 0°C £ CHARACTERISTICS PARAMETER ACTIVE to READ or WRITE delay PRECHARGE command period ...
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Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, and -202) Notes: 1–5, 12–15, 29, 50; notes appear on pages 20–23; 0°C £ CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level ...
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Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, and -202) (Continued) Notes: 1–5, 12–15, 29, 50; notes appear on pages 20–23; 0°C £ CHARACTERISTICS PARAMETER Data valid output window REFRESH to REFRESH ...
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Notes 1. All voltages referenced Tests for AC timing, I characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. ...
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The valid data window is derived by achieving other specifications QHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be ...
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READs and WRITEs with auto precharge are not allowed to be issued until fied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and ...
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The voltage levels used are derived from a mini- mum V level and the referenced test load practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 36. V ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shwon in Figure 12, Data Validity, and Figure ...
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Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes www.DataSheet4U.com MODE Current Address Read Random Address Read Sequential ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: I OUT INPUT LEAKAGE CURRENT: V OUTPUT ...
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... SDRAM Access from Clock, CAS Latency = SDRAM Cycle Time, Latency = 1 26 SDRAM Access From CK , Latency = 1 27 Minimum Row Precharge Time, 09005aef806e1d28 DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN ENTRY (VERSION) MT8VDDT1664HD MT8VDDT3264HD MT8VDDT6464HD 128 256 DDR SDRAM 12,13 9, SSTL 2.5V 6ns(-335) 7ns (-262/-26A) 7.5ns (-265) 8ns (-202) 0 ...
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... Reserved 62 SPD Revision 63 Checksum for Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code 09005aef806e1d28 DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN 128MB, 256MB, 512MB (x64) ENTRY (VERSION) MT8VDDT1664HD MT8VDDT3264HD MT8VDDT6464HD 12ns (-335) 30 15ns (-262/-26A/-265/-202 18ns (-335) 48 RCD 15ns (-262) 3C ...
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... The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. 09005aef806e1d28 DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN ENTRY (VERSION) MT8VDDT1664HD MT8VDDT3264HD MT8VDDT6464HD 01–11 1 set to 7ns (0x70) for optimum BIOS compatibility ...
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R (2X) 0.071 (1.80) (2X) www.DataSheet4U.com 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) NOTE: All dimensions are in inches (millimeters) Data Sheet Designation Released (No Mark): This data sheet contains mini- mum and maximum limits specified over the complete ...