MC10-100ELT22 ON Semiconductor, MC10-100ELT22 Datasheet

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MC10-100ELT22

Manufacturer Part Number
MC10-100ELT22
Description
5VDual TTL to Differential PECL Translator
Manufacturer
ON Semiconductor
Datasheet
translator. Because PECL (Positive ECL) levels are used only +5 V
and ground are required. The small outline 8-lead package and the low
skew, dual gate design of the ELT22 makes it ideal for applications
which require the translation of a clock and a data signal.
October, 2000 – Rev. 4
The MC10ELT/100ELT22 is a dual TTL to differential PECL
For Additional Information, see Application Note AND8003/D
Oxygen Index 28 to 34
1.2 ns Typical Propagation Delay
<300 ps Typical Output to Output Skew
PNP TTL Inputs for Minimal Loading
Flow Through Pinouts
ESD Protection: >2 KV HBM, >200 V MM
Operating Range: V
No Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL–94 code V–0 @ 1/8”,
Transistor Count = 51 devices
Semiconductor Components Industries, LLC, 2000
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q1
Q0
Q1
Q0
* Output state undetermined when inputs are open.
PIN
Qn, Qn
Dn
V
GND
CC
1
2
3
4
PECL
CC
= 4.75 V to 5.25 V with GND= 0 V
PIN DESCRIPTION
FUNCTION
PECL Differential Outputs*
TTL Inputs
Positive Supply
Ground
TTL
8
7
6
5
V
D0
D1
GND
CC
1
*For additional information, see Application Note
MC10ELT22D
MC10ELT22DR2
MC100ELT22D
MC100ELT22DR2
MC10ELT22DT
MC10ELT22DTR2
MC100ELT22DT
MC100ELT22DTR2 TSSOP–8
AND8002/D
H = MC10
K = MC100
A = Assembly Location
CASE 948R
DT SUFFIX
CASE 751
D SUFFIX
TSSOP–8
8
Device
8
SO–8
ORDERING INFORMATION
1
1
http://onsemi.com
TSSOP–8
TSSOP–8
TSSOP–8
Package
SO–8
SO–8
SO–8
SO–8
8
1
8
1
Publication Order Number:
HLT22
ALYW
ALYW
HT22
L = Wafer Lot
Y = Year
W = Work Week
DIAGRAMS*
MARKING
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
98 Units/Rail
98 Units/Rail
98 Units/Rail
98 Units/Rail
MC10ELT22/D
Shipping
8
1
8
1
KLT22
ALYW
ALYW
KT22

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MC10-100ELT22 Summary of contents

Page 1

... The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. ...

Page 2

... Output parameters vary 1:1 with Outputs are terminated through a 50 ohm resistor to V MC10ELT22, MC100ELT22 Condition 1 GND = 0 V GND = 0 V Continuous Surge ...

Page 3

... Output Rise/Fall Time r f (20–80%) 1. Specifications for standard TTL input signal. Driver Device Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) MC10ELT22, MC100ELT22 – Condition ...

Page 4

... Resource Reference of Application Notes AN1400 MC10/100H640 Clock Driver Family I/O SPICE Modeling Kit – AN1404 ECLinPS Circuit Performance at Non–Standard V – AN1405 ECL Clock Distribution Techniques – AN1406 Designing with PECL (ECL at +5.0 V) – AN1503 – ECLinPS I/O SPICE Modeling Kit AN1504 Metastability and the ECLinPS Family – ...

Page 5

... –Y– –Z– MC10ELT22, MC100ELT22 PACKAGE DIMENSIONS SO–8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–07 ISSUE http://onsemi.com ...

Page 6

... MC10ELT22, MC100ELT22 K 8x REF L –U– PIN 1 IDENT A –V– C –T– PACKAGE DIMENSIONS TSSOP–8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R–02 ISSUE DETAIL E –W– DETAIL E http://onsemi.com ...

Page 7

... Notes MC10ELT22, MC100ELT22 http://onsemi.com 7 ...

Page 8

... English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, UK, Ireland MC10ELT22, MC100ELT22 CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com Toll– ...

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