MC10EP195 ON Semiconductor, MC10EP195 Datasheet

MC10EP195

Manufacturer Part Number

MC10EP195

Description

(MC100EP195 / MC10EP195) 3.3V ECL Programmable Delay Chip

Manufacturer

ON Semiconductor

Datasheet

1.MC10EP195.pdf (20 pages)

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MC10EP195, MC100EP195

3.3V ECL Programmable

Delay Chip

designed primarily for clock deskewing and timing adjustment. It

provides variable delay of a differential NECL/PECL input transition.

multiplexers as shown in the logic diagram, Figure 2. The delay

increment of the EP195 has a digitally selectable resolution of about

10 ps and a net range of up to 10.2 ns. The required delay is selected by

the 10 data select inputs D[9:0] values and controlled by the LEN

(pin 10). A LOW level on LEN allows a transparent LOAD mode of

real time delay values by D[9:0]. A LOW to HIGH transition on LEN

will LOCK and HOLD current values present against any subsequent

changes in D[10:0]. The approximate delay values for varying tap

numbers correlating to D0 (LSB) through D9 (MSB) are shown in

Table 6 and Figure 3.

fixed minimum delay of 2.2 ns. An additional pin D10 is provided for

controlling Pins 14 and 15, CASCADE and CASCADE, also latched

by LEN, in cascading multiple PDCs for increased programmable

range. The cascade logic allows full control of multiple PDCs.

Switching devices from all “1” states on D[0:9] with SETMAX LOW

to all “0” states on D[0:9] with SETMAX HIGH will increase the

delay equivalent to “D0”, the minimum increment.

combinations of interconnects between V

for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input

levels, leave V

supply reference to V

voltage to V

between V

this device only. For single-ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

October, 2004 − Rev. 13

The MC10/100EP195 is a Programmable Delay Chip (PDC)

The delay section consists of a programmable matrix of gates and

Because the EP195 is designed using a chain of multiplexers it has a

Select input pins D[10:0] may be threshold controlled by

The V

The 100 Series contains temperature compensation.

Maximum Input Clock Frequency >1.2 GHz Typical

Programmable Range: 0 ns to 10 ns

Delay Range: 2.2 ns to 12.2 ns

10 ps Increments

PECL Mode Operating Range:

NECL Mode Operating Range:

Semiconductor Components Industries, LLC, 2004

(pins 7 and 8). For LVTTL level operation, connect a 1.5 V

may also rebias AC coupled inputs. When used, decouple V

via a 0.01 mF capacitor and limit current sourcing or sinking

pin, an internally generated voltage supply, is available to

and V

pin can be accomplished by placing a 2.2 kW resistor

= 3.0 V to 3.6 V with V

= 0 V with V

and V

for a 3.3 V power supply.

and leave open V

open. For ECL operation, short V

should be left open.

= −3.0 V to −3.6 V

as a switching reference voltage.

= 0 V

pin. The 1.5 V reference

(pin 7) and V

(pin 8)

and

Open Input Default State

Safety Clamp on Inputs

A Logic High on the EN Pin Will Force Q to Logic

Low

D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL

Inputs

Output Reference Voltage

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

*For additional marking information, refer to

Application Note AND8002/D.

CASE 873A

FA SUFFIX

LQFP−32

ORDERING INFORMATION

XXX

http://onsemi.com

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

Publication Order Number:

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DIAGRAM*

MARKING

AWLYYWW

MCXXX

EP195

MC10EP195/D

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