MC14001 Motorola, MC14001 Datasheet

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MC14001

Manufacturer Part Number
MC14001
Description
B-Suffix Series CMOS Gates
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
UB-Suffix Series CMOS Gates
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
REV 3
1/94
MC14001UB
18
12
13
The UB Series logic gates are constructed with P and N channel
Motorola, Inc. 1995
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
1
2
5
6
8
9
10
12
11
2
3
4
5
9
Quad 2–Input
Dual 4–Input
MC14001UB
MC14012UB
NAND Gate
NOR Gate
NC = 6, 8
1
13
3
4
10
11
LOGIC DIAGRAMS
10
12
11
12
13
11
2
3
4
5
9
1
2
8
3
4
5
FOR ALL DEVICES
Triple 3–Input
Dual 4–Input
MC14002UB
MC14023UB
V DD = PIN 14
NAND Gate
V SS = PIN 7
NOR Gate
NC = 6, 8
9
6
10
1
13
11
12
13
12
13
1
2
8
3
4
5
1
2
5
6
8
9
Quad 2–Input
Triple 3–Input
MC14025UB
MC14011UB
NAND Gate
NOR Gate
3
4
10
11
9
6
10
Triple 3-Input NAND Gate
Quad 2-Input NAND Gate
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
to the range V SS
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
Dual 4-Input NAND Gate
Triple 3-Input NOR Gate
Quad 2-Input NOR Gate
Dual 4-Input NOR Gate
This device contains protection circuitry to
Unused inputs must always be tied to an
T A = – 55 to 125 C for all packages.
MC14001UB
MC14002UB
MC14011UB
MC14012UB
MC14023UB
MC14025UB
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
MOTOROLA CMOS LOGIC DATA
v
(V in or V out )
CASE 751A
CERAMIC
CASE 632
CASE 646
D SUFFIX
L SUFFIX
P SUFFIX
PLASTIC
Plastic
Ceramic
SOIC
SOIC
v
V DD .

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MC14001 Summary of contents

Page 1

... For proper operation and V out should be constrained to the range V SS Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Unused outputs must be left open. MC14001UB MC14002UB MC14011UB MC14012UB MC14023UB MC14025UB L SUFFIX ...

Page 2

... OUT MC14025UB Triple 3–Input NOR Gate OUT C OUT OUT MC14001UB 19 ...

Page 3

... (50 pF – 50) Vfk where (per package pF – volts kHz is input frequency, and k = 0.001 x the number of exercised gates per package. MC14001UB 20 Î Î Î Î Î Î Î Î Î ...

Page 4

... IC’s potential performance INPUT PULSE GENERATOR * 7 * All unused inputs of AND, NAND gates must be connected All unused inputs of OR, NOR gates must be connected Figure 1. Switching Time Test Circuit and Waveforms MC14001UB CIRCUIT SCHEMATIC MOTOROLA CMOS LOGIC DATA Î ...

Page 5

... Vdc c b – 8.0 a – 10 – 10 – 8.0 – 6.0 – 4 DRAIN VOLTAGE (Vdc) Figure 4. Typical Output Source Characteristics MC14001UB 22 MC14012UB CIRCUIT SCHEMATIC (1/2 of Device Shown Vdc Unused input 14 connected ...

Page 6

... FLASH. 4. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC 0.015 0.039 0.39 1.01 MC14001UB 23 ...

Page 7

... MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 are registered MOTOROLA CMOS LOGIC DATA MC14001UB/D ...

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