MC14001UB ON Semiconductor, MC14001UB Datasheet

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MC14001UB

Manufacturer Part Number
MC14001UB
Description
UB-Suffix Series CMOS Gates
Manufacturer
ON Semiconductor
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC14001UBCL
Manufacturer:
MOTOROLA
Quantity:
24
Part Number:
MC14001UBCP
Manufacturer:
minicircuits
Quantity:
5
Part Number:
MC14001UBCP
Manufacturer:
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Quantity:
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MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting non–buffered functions.
1. Maximum Ratings are those values beyond which damage to the device
2. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The UB Series logic gates are constructed with P and N channel
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
Suffix Devices
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series UB
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 2.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 1.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
MC14001UBCP
MC14001UBD
MC14001UBDR2
MC14011UBCP
MC14011UBD
MC14011UBDR2
Device
Quad 2–Input NAND Gate
Quad 2–Input NOR Gate
XX
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
http://onsemi.com
MC14001UB
MC14011UB
CASE 751A
= Specific Device Code
= Assembly Location
CASE 646
P SUFFIX
D SUFFIX
PDIP–14
SOIC–14
Package
SOIC–14
SOIC–14
SOIC–14
SOIC–14
PDIP–14
PDIP–14
Publication Order Number:
2500/Tape & Reel
2500/Tape & Reel
14
14
MC140XXUBCP
1
1
DIAGRAMS
MC14001UB/D
MARKING
AWLYYWW
AWLYWW
Shipping
2000/Box
2000/Box
140XXU
55/Rail
55/Rail

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MC14001UB Summary of contents

Page 1

... MC14001UB, MC14011UB UB-Suffix Series CMOS Gates The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. The UB set of CMOS gates are inverting non–buffered functions. ...

Page 2

... MC14001UB, MC14011UB LOGIC DIAGRAMS MC14001UB Quad 2–Input NOR Gate PIN PIN 7 SS FOR ALL DEVICES PIN ASSIGNMENTS MC14001UB Quad 2–Input NOR Gate OUT OUT ...

Page 3

... Vfk where (per package pF per package. MC14001UB, MC14011UB (Voltages Referenced Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î – Î ...

Page 4

... AND, NAND gates must be connected All unused inputs of OR, NOR gates must be connected Figure 1. Switching Time Test Circuit and Waveforms MC14001UB, MC14011UB = pF Î Î Î Î Î Î Î Î Î Vdc Î ...

Page 5

... MC14001UB CIRCUIT SCHEMATIC Vdc Vdc 10 8.0 b 6.0 5.0 Vdc 2.0 4.0 6.0 8 INPUT VOLTAGE (Vdc) in Figure 2. Typical Voltage and Current Transfer Characteristics – 5.0 Vdc GS – 2 – ...

Page 6

... MC14001UB, MC14011UB –T– SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN B FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 7

... –T– SEATING 14 PL PLANE 0.25 (0.010 MC14001UB, MC14011UB PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE 0.25 (0.010 http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 8

... English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland MC14001UB, MC14011UB CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – ...

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