MC14043B ON Semiconductor, MC14043B Datasheet

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MC14043B

Manufacturer Part Number
MC14043B
Description
CMOS MSI(Quad R-S Latches)
Manufacturer
ON Semiconductor
Datasheet

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MC14043B, MC14044B
CMOS MSI
Quad R–S Latches
with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three–state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
2. Maximum Ratings are those values beyond which damage to the device
3. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14043B and MC14044B quad R–S latches are constructed
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Low–Power Schottky TTL Load Over the Rated Temperature Range
Double Diode Input Protection
Three–State Outputs with Common Enable
Outputs Capable of Driving Two Low–power TTL Loads or One
Supply Voltage Range = 3.0 Vdc to 18 Vdc
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 2.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
1. For ordering information on the EIAJ version of
MC14043BCP
MC14043BD
MC14043BDR2
MC14043BF
MC14043BFEL
MC14044BCP
MC14044BD
MC14044BDR2
the SOIC packages, please contact your local
ON Semiconductor representative.
Device
XX
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
http://onsemi.com
= Specific Device Code
= Assembly Location
CASE 751B
SOEIAJ–16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
SOIC–16
PDIP–16
SOEIAJ–16
SOEIAJ–16
SOIC–16
SOIC–16
SOIC–16
SOIC–16
Package
PDIP–16
PDIP–16
Publication Order Number:
2500/Tape & Reel
2500/Tape & Reel
16
16
16
1
1
1
MC140XXBCP
DIAGRAMS
MARKING
See Note 1.
See Note 1.
AWLYYWW
MC140XXB
AWLYWW
AWLYWW
Shipping
2000/Box
2400/Box
2000/Box
2400/Box
MC14043B/D
140XXB

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MC14043B Summary of contents

Page 1

... MC14043B, MC14044B CMOS MSI Quad R–S Latches The MC14043B and MC14044B quad R–S latches are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three–state buffers having a common enable input. The outputs are enabled with a logical “ ...

Page 2

... TRUTH TABLE ENABLE X = Don’t Care MC14043B, MC14044B PIN ASSIGNMENT CONNECTION MC14044B PIN PIN PIN 13 ...

Page 3

... I (50 pF – 50) Vfk where (per package pF MC14043B, MC14044B (Voltages Referenced Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î – Î ...

Page 4

... SET 10 90% 50% RESET 10% t THL Q 10% t PHL MC14043B, MC14044B = pF Î Î Î Î Î Î Î Î Î Î Î Î Î Vdc Symbol Î Î Î Î Î Î Î Î Î Î ...

Page 5

... Set, Reset, Enable, and Switch Conditions for 3–State Tests Test Enable Open Closed A PZH t Closed Open B PZL t Open Closed A PHZ t Closed Open B PLZ ENABLE MC14043B, MC14044B MC14043B MC14044B OUTPUT UNDER DD ...

Page 6

... G K –T– SEATING PLANE 0.25 (0.010 MC14043B, MC14044B PACKAGE DIMENSIONS PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R L SEATING –T– PLANE SOIC–16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B– ...

Page 7

... PLASTIC EIAJ SOIC PACKAGE VIEW 0.10 (0.004) 0.13 (0.005) M MC14043B, MC14044B PACKAGE DIMENSIONS SOEIAJ–16 F SUFFIX CASE 966–01 ISSUE O NOTES DETAIL P c http://onsemi.com 7 DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 8

... English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland MC14043B, MC14044B CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – ...

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