MC145151 Motorola, MC145151 Datasheet - Page 10

• Manufacturer Part Number: MC145151
• Description: Parallel-Input PLL Frequency Synthesizer
• Manufacturer: Motorola

INPUT PINS
f in
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (PDIP – Pins 18, 1, 2;
SOG – Pins 20, 1, 2)
possible divide values for the total reference divider, as
defined by the table below:
CLK, DATA
Shift Register Clock, Serial Data Inputs
(PDIP – Pins 10, 11; SOG – Pins 11, 12)
16–bit shift register. The Data input provides programming
MC145151–2 through MC145158–2
10
Input to the
These three inputs establish a code defining one of eight
Each low–to–high transition clocks one bit into the on–chip
OSC out
REF out
OSC in
DATA
ENB
CLK
RA2
f in
0
0
0
0
1
1
1
1
Reference Address Code
N portion of the synthesizer. f in is typically
PIN DESCRIPTIONS
RA1
0
0
1
1
0
0
1
1
V DD
RA0
0
1
0
1
0
1
0
1
Divide
Divide
RA2
RA1
RA0
Value
Value
Total
1024
2048
3668
4096
6144
8192
MC145155–2 BLOCK DIAGRAM
512
16
14 x 8 ROM REFERENCE DECODER
14–BIT SHIFT REGISTER
14–BIT
14–BIT
information for the 14–bit N counter and the two switch sig-
nals SW1 and SW2. The entry format is as follows:
ENB
Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
ister into the latches, and to the programmable counter in-
puts, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up esta-
blishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (PDIP – Pins 17, 16;
SOG – Pins 19, 18)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC out .
When high (1), ENB transfers the contents of the shift reg-
These pins form an on–chip reference oscillator when con-
LATCH
LAST DATA BIT IN (BIT NO. 16)
R COUNTER
N COUNTER
14
14
14
N COUNTER BITS
FIRST DATA BIT IN (BIT NO. 1)
f R
f V
2–BIT SHIFT
REGISTER
DETECTOR
DETECTOR
DETECT
LATCH
PHASE
PHASE
LOCK
B
A
MOTOROLA
LD
PD out
SW2
SW1
V
R