MC145151 Motorola, MC145151 Datasheet - Page 11

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MC145151

Manufacturer Part Number
MC145151
Description
Parallel-Input PLL Frequency Synthesizer
Manufacturer
Motorola
Datasheet

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OUTPUT PINS
PD out
Phase Detector A Output (PDIP, SOG – Pin 6)
signal. Double–ended outputs are also available for this pur-
pose (see V and R ).
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
for a loop–error signal. A single–ended output is also avail-
able for this purpose (see PD out ).
leading, then error information is provided by V pulsing low.
lagging, then error information is provided by R pulsing low.
period when both pulse low in phase.
LD
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
phase and frequency). LD pulses low when loop is out of
lock.
MOTOROLA
R , V
R remains essentially high.
V remains essentially high.
V and R remain high except for a small minimum time
Three–state output of phase detector for use as loop error
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Imped-
These phase detector outputs can be combined externally
If frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
Essentially a high level when loop is locked (f R , f V of same
ance State
* The R and V outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
for additional information. The R and V outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
FRONT END
TUNER OR
UHF/VHF
CATV
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
PRESCALER
MC12073/74
KEYBOARD
TYPICAL APPLICATIONS
f in
DATA
MC145155–2
CLK
4.0 MHz
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14;
SOG – Pins 14, 15)
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
15 V, independent of the V DD supply voltage. These are
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
REF out
Buffered Reference Oscillator Output (PDIP, SOG –
Pin 15)
nally provided reference–input signal.
POWER SUPPLY
V DD
Positive Power Supply (PDIP, SOG – Pin 5)
from + 3 to + 9 V with respect to V SS .
V SS
Negative Power Supply (PDIP, SOG – Pin 7)
ground.
MPU/MCU
SW1 and SW2 provide latched open–drain outputs corre-
Buffered output of on–chip reference oscillator or exter-
The positive power supply potential. This pin may range
The most negative supply potential. This pin is usually
CMOS
ENB
R
V
MC145151–2 through MC145158–2
3
LED DISPLAY
MC14489
+
1/2 MC1458*
11

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