MC145151 Motorola, MC145151 Datasheet - Page 14

• Manufacturer Part Number: MC145151
• Description: Parallel-Input PLL Frequency Synthesizer
• Manufacturer: Motorola

INPUT PINS
f in
Frequency Input (Pin 10)
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels), dc coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 20, 1, 2)
possible divide values for the total reference divider, as
defined by the table below:
CLK, DATA
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
19–bit shift register. The data input provides programming in-
formation for the 10–bit
and the two switch signals SW1 and SW2. The entry format
is as follows:
MC145151–2 through MC145158–2
14
f in is typically derived from a dual–modulus prescaler and is
Input to the positive edge triggered
These three inputs establish a code defining one of eight
Each low–to–high transition clocks one bit into the on–chip
OSC out
REF out
OSC in
DATA
ENB
CLK
MC
RA2
f in
0
0
0
0
1
1
1
1
Reference Address Code
V DD
PIN DESCRIPTIONS
RA1
0
0
1
1
0
0
1
1
N counter, the 7–bit
RA2
RA1
RA0
RA0
0
1
0
1
0
1
0
1
7–BIT SHIFT REGISTER
7–BIT
N and
A COUNTER LATCH
Divide
Divide
Value
Value
Total
1000
1024
2048
A COUNTER
MC145156–2 BLOCK DIAGRAM
128
256
640
12 x 8 ROM REFERENCE DECODER
64
8
A counters.
7
7
A counter,
12–BIT
CONTROL LOGIC
R COUNTER
12
ENB
Latch Enable Input (Pin 13)
ister into the latches, and to the programmable counter in-
puts, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up esta-
blishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 19, 18)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC out .
TEST
Factory Test Input (Pin 16)
When high (1), ENB transfers the contents of the shift reg-
These pins form an on–chip reference oscillator when con-
Used in manufacturing. Must be left open or tied to V SS .
10–BIT SHIFT REGISTER
10–BIT
A COUNTER BITS
N COUNTER LATCH
LAST DATA BIT IN (BIT NO. 19)
N COUNTER
10
10
FIRST DATA BIT IN (BIT NO. 1)
f R
f V
N COUNTER BITS
2–BIT SHIFT
REGISTER
DETECTOR
DETECTOR
DETECT
LATCH
PHASE
PHASE
LOCK
B
A
MOTOROLA
LD
PD out
SW2
SW1
V
R