MC145151 Motorola, MC145151 Datasheet - Page 15

• Manufacturer Part Number: MC145151
• Description: Parallel-Input PLL Frequency Synthesizer
• Manufacturer: Motorola

OUTPUT PINS
PD out
Phase Detector A Output (Pin 6)
signal. Double–ended outputs are also available for this pur-
pose (see V and R ).
Phase Detector B Outputs (Pins 4, 3)
for a loop–error signal. A single–ended output is also avail-
able for this purpose (see PD out ).
leading, then error information is provided by V pulsing low.
lagging, then error information is provided by R pulsing low.
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 8)
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the
programmed value. At this time, MC goes high and remains
high until the
down from its programmed value (N – A additional counts
since both N and
tion of the cycle). MC is then set back low, the counters
MOTOROLA
R , V
R remains essentially high.
V remains essentially high.
V and R remain high except for a small minimum time
Three–state output of phase detector for use as loop–error
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Imped-
These phase detector outputs can be combined externally
If frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
Signal generated by the on–chip control logic circuitry for
ance State
N counter has counted the rest of the way
A are counting down during the first por-
A counter has counted down from its
preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
divide value (N T ) = N
dual–modulus prescaler divide values respectively for high
and low MC levels, N the number programmed into the
counter, and A the number programmed into the
LD
Lock Detector Output (Pin 9)
phase and frequency). LD pulses low when loop is out of
lock.
SW1, SW2
Band Switch Outputs (Pins 14, 15)
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
15 V, independent of the V DD supply voltage. These are
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
REF out
Buffered Reference Oscillator Output (Pin 17)
nally provided reference–input signal.
POWER SUPPLY
V DD
Positive Power Supply (Pin 5)
from + 3 to + 9 V with respect to V SS .
V SS
Negative Power Supply (Pin 7)
ground.
Essentially a high level when loop is locked (f R , f V of same
SW1 and SW2 provide latched open–drain outputs corre-
Buffered output of on–chip reference oscillator or exter-
The positive power supply potential. This pin may range
The most negative supply potential. This pin is usually
MC145151–2 through MC145158–2

P + A where P and P + 1 represent the
A counter.
15
N