MC145151 Motorola, MC145151 Datasheet - Page 21

• Manufacturer Part Number: MC145151
• Description: Parallel-Input PLL Frequency Synthesizer
• Manufacturer: Motorola

INPUT PINS
f in
Frequency Input (Pin 8)
this input decrements the
has an inverter biased in the linear region to allow use with
ac coupled signals as low as 500 mV p–p. For larger ampli-
tude signals (standard CMOS logic levels), dc coupling may
be used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
MOTOROLA
A,
Input frequency from VCO output. A rising edge signal on
Each low–to–high transition of the CLK shifts one bit of
OSC out
REF out
OSC in
DATA
ENB
CLK
N counter latch. The data entry format is as follows:
f in
CONTROL
PIN DESCRIPTIONS
FIRST DATA BIT INTO SHIFT REGISTER
1–BIT
S/R
A and
R
N counters. This input
MC145158–2 BLOCK DIAGRAM
COUNTER
7–BIT
A COUNTER
7–BIT S/R
LATCH
REFERENCE COUNTER LATCH
7
7
14–BIT SHIFT REGISTER
14–BIT
A
CONTROL LOGIC
ENB
Latch Enable Input (Pin 11)
ter into the reference divider or N, A latches depending on
the control bit. The reference divider latches are activated if
the control bit is at a logic high and the
activated if the control bit is at a logic low. A logic low on this
pin allows the user to change the data in the shift registers
without affecting the counters. ENB is normally low and is
pulsed high to transfer data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 1, 2)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS log-
ic levels) dc coupling may also be used. In the external refer-
ence mode, no connection is required to OSC out .
A logic high on this pin latches the data from the shift regis-
These pins form an on–chip reference oscillator when con-
R COUNTER
14
14
10–BIT
COUNTER
10–BIT S/R
N COUNTER
LATCH
A
10
10
FIRST DATA BIT INTO SHIFT REGISTER
MC145151–2 through MC145158–2
N
DETECTOR
DETECTOR
DETECT
PHASE
PHASE
LOCK
A
B
N
N,
A latches are
f R
LD
PD out
f V
MC
V
R
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