MC14572UB ON Semiconductor, MC14572UB Datasheet

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MC14572UB

Manufacturer Part Number
MC14572UB
Description
Hex Gate
Manufacturer
ON Semiconductor
Datasheet

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MC14572UB
Hex Gate
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
2. Maximum Ratings are those values beyond which damage to the device
3. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14572UB hex functional gate is constructed with MOS
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Inverter
Application
Schottky TTL Load over the Rated Temperature Range
Diode Protection on All Inputs
Single Supply Operation
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NOR Input Pin Adjacent to V
NAND Input Pin Adjacent to V
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
NAND Output Pin Adjacent to Inverter Input Pin For AND
Capable of Driving Two Low–power TTL Loads or One Low–Power
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
SS
DD
DD
.
Pin to Simplify Use As An Inverter
Pin to Simplify Use As An
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 2.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
1. For ordering information on the EIAJ version of
MC14572UBCP
MC14572UBD
MC14572UBDR2
MC14572UBF
MC14572UBFEL
the SOIC packages, please contact your local
ON Semiconductor representative.
Device
ORDERING INFORMATION
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
http://onsemi.com
CASE 751B
SOEIAJ–16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
SOIC–16
SOEIAJ–16
SOEIAJ–16
PDIP–16
= Assembly Location
Package
SOIC–16
SOIC–16
PDIP–16
Publication Order Number:
2500/Tape & Reel
16
16
16
1
1
1
MC14572UBCP
DIAGRAMS
MC14572UB
MC14572UB/D
MARKING
See Note 1.
See Note 1.
AWLYYWW
AWLYWW
AWLYWW
Shipping
2000/Box
14572U
48/Rail

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MC14572UB Summary of contents

Page 1

... MC14572UB Hex Gate The MC14572UB hex functional gate is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. The chip contains four inverters, one NOR gate and one NAND gate ...

Page 2

... MC14572UB PIN ASSIGNMENT OUT OUT OUT LOGIC DIAGRAM PIN PIN 8 SS CIRCUIT SCHEMATIC http://onsemi.com ...

Page 3

... The formulas given are for the typical characteristics only calculate total supply current at loads other than 50 pF (50 pF – 50) Vfk where (per package pF MC14572UB (Voltages Referenced – Vdc Min Max Min V 5.0 — 0.05 — ...

Page 4

... Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance INPUT 2 PULSE GENERATOR INPUT 15 PULSE GENERATOR Figure 1. Switching Time Test Circuits and Waveforms MC14572UB = pF Symbol TLH 5 THL 5 PLH t 5 ...

Page 5

... SEATING –T– PLANE 0.25 (0.010 MC14572UB PDIP–16 P SUFFIX NOTES: CASE 648–08 1. DIMENSIONING AND TOLERANCING PER ANSI ISSUE R Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 6

... G K –T– SEATING PLANE 0.25 (0.010 MC14572UB PACKAGE DIMENSIONS SOIC–16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE 0.25 (0.010 http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 7

... PLASTIC EIAJ SOIC PACKAGE VIEW 0.10 (0.004) 0.13 (0.005) M MC14572UB PACKAGE DIMENSIONS SOEIAJ–16 F SUFFIX CASE 966–01 ISSUE O NOTES DETAIL P c http://onsemi.com 7 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC14572UB/D ...

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