ISL6532B Intersil Corporation, ISL6532B Datasheet

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ISL6532B

Manufacturer Part Number
ISL6532B
Description
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
Manufacturer
Intersil Corporation
Datasheet
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532B provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply V
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (V
need for a negative supply. A buffered version of the V
reference is provided as V
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings V
in a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD
signal indicates that all supplies are within spec and
operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the V
regulators. Thermal shutdown is integrated.
Pinout
5VSBY
VDDQ
GND
VTT
VTT
DDQ
1
2
3
4
5
/2) high current V
20 19 18 17 16
ISL6532B (QFN)
6
TOP VIEW
®
REF
7
±
1
8
2% over line, load, and
.
DDQ
9
Data Sheet
TT
with high current during
TT
10
and V
DDQ
voltage without the
15
14
13
12
11
NCH
PGOOD
GND
COMP
FB
into regulation
DDQ
standby
DDQ
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
/2
Ordering Information
Features
• Generates 2 Regulated Voltages
• ACPI Compliant Sleep State Control
• Integrated V
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection on V
• Integrated Thermal Shutdown Protection
• QFN Package Option
Applications
• Single and Dual Channel DDR Memory Power Systems in
• Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
ISL6532BCR
PART NUMBER
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
- Glitch-free Transitions During State Changes
- Both Outputs:
to 0.8V supports DDR and DDR2 Specifications
Monitoring of Both Outputs
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
- QFN Near Chip Scale Package Footprint; Improves
ACPI compliant PCs
Accurate V
Flat No Leads - Product Outline
PCB Efficiency, Thinner in Profile
December 2003
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
REF
DDQ
TEMP. RANGE
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
±
Buffer
/2 Divider Reference
2% Over Temperature
0 to 70
(
o
C)
TT
20 Ld 6x6 QFN
PACKAGE
and Under/Over-Voltage
ISL6532B
FN9120.2
L20.6x6
PKG. DWG. #

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ISL6532B Summary of contents

Page 1

... Data Sheet ACPI Regulator/Controller for Dual Channel DDR Memory Systems The ISL6532B provides a complete ACPI compliant power solution for DIMM dual channel DDR/DDR2 memory systems. Included are both a synchronous buck controller and integrated LDO to supply V with high current during DDQ S0/S1 states and standby current during S3 state ...

Page 2

Block Diagram P3V3SBY VDDQ S3 REGULATOR VDDQ(2) VTTSNS VTT REG VTT(2) DISABLE { R U VREF_IN { R L UV/OV VREF_OUT SLP_S3# SLP_S5# 5VSBY VOLTAGE REFERENCE 0.800V 0.680V (-15%) 0.920V (+15%) 5V POR S3 SLEEP, SOFT-START, PGOOD, AND FAULT PWM ...

Page 3

... C VTT 3 ISL6532B 12V 5VSBY SLEEP STATE LOGIC PWM CONTROLLER STANDBY LDO ISL6532B VTT REGULATOR 5VSBY +12V C BP S3# NCH S5# VREF_OUT VREF_IN UGATE + C SS ISL6532B LGATE VTT VDDQ VTT VDDQ VTTSNS FB COMP GND DDQ + Q2 V REF +5V OR +3.3V R NCH + DDQ L 2 ...

Page 4

... Typical Application - Input From 5V Dual +3.3V PGOOD V DDQ SLP_S3 SLP_S5 V REF VTT 4 ISL6532B 5VSBY +12V C BP S3# NCH S5# VREF_OUT VREF_IN UGATE C SS ISL6532B LGATE VTT VDDQ VTT VDDQ VTTSNS FB COMP GND 5V DUAL R NCH + DDQ L 2.5V OUT + Q2 C VDDQ ...

Page 5

... PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate STATE LOGIC S3# Transition Level S5# Transition Level 5 ISL6532B Thermal Information Thermal Resistance (Typical, Notes 1, 2) QFN Package . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package 150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s 300 o ...

Page 6

... VDDQ UV Level Thermal Shutdown Limit Functional Pin Description 5VSBY (Pin 1) 5VSBY is the bias supply of the ISL6532B typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6532B enters a reduced power mode and draws less than 1mA (I 5VSBY supply. This pin should be locally bypassed using a 0.1µ ...

Page 7

... ACPI compliance is realized through the SLP_S3 and SLP_S5 sleep signals and through monitoring of the 12V ATX bus. Initialization The ISL6532B automatically initializes upon receipt of input power. Special sequencing of the input supplies is not ||R ), sets the necessary. The Power-On Reset (POR) function continually ...

Page 8

... ACPI State Transitions Cold Start (S5/ Transition) At the onset of a mechanical start, the ISL6532B receives it’s bias voltage from the 5V Standby bus (5VSBY). As soon as the SLP_S3 and SLP_S5 signals have transitioned HIGH, the ISL6532B starts an internal counter. Following a cold start or any subsequent S5 state, state transitions are ignored until the system enters S0/S1 ...

Page 9

... Over Current Protection TT The internal V LDO is protected from fault conditions TT through a 3.3A current limit. This current limit protects the ISL6532B if the LDO is sinking or sourcing current. During an overcurrent event on the V LDO, only the V TT disabled. Once the over current condition on the V removed, V will recover. ...

Page 10

... There are two sets of critical components in the ISL6532B switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling ...

Page 11

... FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN AND OUTPUT VOLTAGE SELECTION The compensation network consists of the error amplifier (internal to the ISL6532B) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin ...

Page 12

... Given a sufficiently fast control loop design, the ISL6532B will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...

Page 13

... IN recovery of the upper and lower MOSFET’s body diode. The gate-charge losses are dissipated in part by the ISL6532B and do not significantly heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both ...

Page 14

... C 19 0.47µF V DDQ + 220µF 1.25V + C 21 220µF FIGURE 7. DDR SDRAM AND AGP VOLTAGE REGULATOR USING THE ISL6532B 14 ISL6532B of-Materials and circuit board description, can be found in Application Note AN1055. 5VSBY VCC12 C 17,18 1µ 1µF PGOOD NCH SLP_S5# ...

Page 15

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 ISL6532B L20.6x6 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJB ISSUE C) ...

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