ISL6561 Intersil Corporation, ISL6561 Datasheet
ISL6561
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ISL6561 Summary of contents
Page 1
... Eliminating ground differences improves regulation and protection accuracy. The threshold- sensitive enable input is available to accurately coordinate the start up of the ISL6561 with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting ...
Page 2
... ISL6561CR Block Diagram VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET REF DAC VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB IDROOP TCOMP T 2 ISL6561 OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT START CLOCK AND AND SAWTOOTH FAULT LOGIC ...
Page 3
... PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- OFS PWM4 FS ISEN4+ ISEN4 TCOMP GND EN +12V 3 ISL6561 +12V VCC PVCC HIP6601B DRIVER PWM +5V +12V VCC PVCC HIP6601B PWM DRIVER +12V VCC BOOT PVCC HIP6601B PWM DRIVER +12V VCC ...
Page 4
... PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- OFS PWM4 FS ISEN4+ ISEN4 TCOMP GND EN +12V 4 ISL6561 +12V VCC PVCC HIP6601B DRIVER PWM +5V +12V VCC PVCC HIP6601B PWM DRIVER +12V VCC BOOT PVCC HIP6601B PWM DRIVER +12V VCC ...
Page 5
... PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- OFS PWM4 FS ISEN4+ ISEN4 GND TCOMP EN +12V 5 ISL6561 +12V VCC PVCC HIP6601B PWM DRIVER +5V +12V VCC PVCC HIP6601B PWM DRIVER +12V VCC BOOT PVCC HIP6601B PWM DRIVER +12V VCC ...
Page 6
... PWM1 PWM2 VID2 ISEN2+ VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- OFS PWM4 ISEN4+ FS ISEN4 TCOMP GND EN +12V 6 ISL6561 +12V VCC PVCC HIP6601B DRIVER PWM +5V +12V VCC PVCC HIP6601B PWM DRIVER +12V VCC BOOT PVCC HIP6601B PWM DRIVER +12V VCC ...
Page 7
... VID Pull Up VID Input Low Level VID Input High Level DAC Source/Sink Current REF Source/Sink Current PIN-ADJUSTABLE OFFSET Voltage at OFS pin 7 ISL6561 Thermal Information Thermal Resistance + 0.3V QFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s 300 ...
Page 8
... When using the internal shunt regulator, VCC is clamped to 6.02V (max). Current must be limited to 25mA or less. 4. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 5. During soft start, VDAC rises from 0 to VID. The over-voltage trip level is the higher of 1.7V and VDAC + 0.2V. 8 ISL6561 TEST CONDITIONS R = 100 k ...
Page 9
... Driving EN below 1.14V will clear all fault states and prime the ISL6556 to soft start when re-enabled. ENLL - This pin is implemented in QFN ISL6561 only. It’s a logic-level enable input for the controller. When asserted to a logic high, the ISL6561 is active depending on status of EN, the internal POR, VID inputs and pending fault states ...
Page 10
... The ISL6561 controller helps simplifying the implementation by integrating vital functions and requiring minimal output components. The block diagrams on pages 2 and 3 provide top level views of multi-phase power conversion using the ISL65556ACB and ISL6561CR controllers ...
Page 11
... RMS current for comparison. PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6561 is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1 ...
Page 12
... If the R-C network components are selected such that the R- C time constant matches the inductor L/DCR time constant, then V is equal to the voltage drop across the DCR ISL6561 Inductor R PWM(n) ISL6561 INTERNAL CIRCUIT I n SAMPLE & ISEN- HOLD + - ISEN+ DCR I ...
Page 13
... DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6561 to include the combined tolerances of each of these elements. The output of the error amplifier, V COMP sawtooth waveform to generate the PWM signals ...
Page 14
... R 1 1.4500V FB r DS(ON) 0 1.4625V Output-Voltage Offset Programming 1 1.4750V The ISL6561 allows the designer to accurately adjust the 0 1.4875V offset voltage. When a resistor 1.5000V OFS and VCC, the voltage across it is regulated to 2.0V. This causes a proportional current (I 0 1.5125V R is connected to ground, the voltage across it is ...
Page 15
... The value of the Tcomp resistor can be determined using Equation 13. R TCOMP In Equation 13, K between the ISL6561 and the lower MOSFET or output inductor. It represents how closely the controller temperature and C is required for an ISL6561 REF REF REF ...
Page 16
... The bias voltage applied at VCC must reach the internal is the power-on reset (POR) rising threshold. Once this threshold TC is reached, proper operation of all aspects of the ISL6561 is guaranteed. Hysteresis between the rising and falling or Inductor thresholds assure that once enabled, the ISL6561 will not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications) ...
Page 17
... VID plus 200mV. During soft start, the over-voltage trip level is the higher of 1.7V or VID plus 200mV. Upon successful soft start, the over-voltage trip level is 200mV above VID. Two actions are taken by the ISL6561 to protect the microprocessor load when an over-voltage condition occurs. ...
Page 18
... MOSFETs to turn on. The ISL6561 will continue to protect the load in this fashion as long as the over-voltage condition recurs. Simultaneous to the protective action of the PWM outputs, the OVP pin pulls to VCC delivering up to 100mA to the gate of a crowbar MOSFET or SCR placed either on the input rail or the output rail ...
Page 19
... P V ---- --------- ISL6561 At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t approximate power loss the maximum and OUT IN A third component involves the lower MOSFET’s reverse- recovery charge, Q ...
Page 20
... V the peak-to-peak sawtooth signal amplitude as described in Figure 6 and Electrical Specifications. C (OPTIONAL COMP FB + IOUT DROOP - VDIFF LOAD-LINE REGULATED ISL6561 CIRCUIT , has already been chosen The target 0 1 ------------------- > ...
Page 21
... COMP IOUT VDIFF FIGURE 14. COMPENSATION CIRCUIT FOR ISL6561 BASED CONVERTER WITHOUT LOAD-LINE REGULATION The optional capacitor sometimes needed to bypass 2 noise away from the PWM comparator (see Figure 13). Keep a position available for C , and be prepared to install a high- 2 frequency capacitor of between 22pF and 150pF in case any leading-edge jitter problem is noted ...
Page 22
... C is the total output capacitance, and N is the number of active channels. 22 ISL6561 Input Supply Voltage Selection The VCC input of the ISL6561 can be connected either directly to a +5V supply or through a current limiting resistor (EQ. 27 +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used ...
Page 23
... The result from the high current slew rates produced by the upper MOSFETs turn on 23 ISL6561 and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize suppression. ...
Page 24
... The ISL6561 can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors, R feedback resistor, and compensation components ...
Page 25
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 ISL6561 L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C) ...