ISL6564A Intersil Corporation, ISL6564A Datasheet
ISL6564A
Related parts for ISL6564A
ISL6564A Summary of contents
Page 1
... Eliminating ground differences improves regulation and protection accuracy. The threshold- sensitive enable input is available to accurately coordinate the start up of the ISL6564A with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting ...
Page 2
... Pinout VID5 VID4 VID3 VID2 VID1 VID0 GND OFS IOUT DAC 2 ISL6564A ISL6564A (40 LD QFN) TOP VIEW GND ISEN4+ 29 ISEN4- 28 ISEN2- 27 ISEN2+ 26 PWM2 25 PWM1 24 ISEN1+ ISEN1 ...
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... ISL6564A Block Diagram PGOOD VDIFF RGND x1 VSEN OVP +200mV OFS OFFSET REF DAC VID5 VID4 DYNAMIC VID3 VID VID2 D/A VID1 VID0 COMP FB IDROOP IOUT 3 ISL6564A OVP DRVEN VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT-START CLOCK AND AND SAWTOOTH FAULT LOGIC GENERATOR ∑ ...
Page 4
... ISEN2+ VID2 ISEN2- VID1 PWM3 ISEN3+ VID0 ISEN3- DRVEN OFS PWM4 FS ISEN4+ ISEN4- IOUT GND NTC NETWORK VOLTAGE PROPOTIONAL TO LOAD CURRENT 4 ISL6564A +12V VCC PVCC ISL6612 DRIVER PWM +5V +12V VCC PVCC ISL6612 PWM DRIVER +12V VCC BOOT PVCC ISL6612 DRIVER PWM ...
Page 5
... ISEN2+ VID2 ISEN2- VID1 PWM3 ISEN3+ VID0 ISEN3- DRVEN OFS PWM4 FS ISEN4+ ISEN4- GND IOUT NTC NETWORK VOLTAGE PROPOTIONAL TO LOAD CURRENT 5 ISL6564A +12V VCC PVCC ISL6612 DRIVER PWM +5V +12V VCC PVCC ISL6612 PWM DRIVER +12V VCC BOOT PVCC ISL6612 DRIVER PWM ...
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... VID1 ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- DRVEN OFS PWM4 FS ISEN4+ ISEN4- GND EN IOUT +12V NTC NETWORK VOLTAGE PROPOTIONAL TO LOAD CURRENT 6 ISL6564A DS(ON) +12V VCC PVCC ISL6612 DRIVER PWM +5V +12V VCC PVCC ISL6612 DRIVER PWM +12V VCC BOOT PVCC ISL6612 DRIVER PWM ...
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... ISEN2- VID0 PWM3 ISEN3+ VID12.5 ISEN3- DRVEN OFS PWM4 FS ISEN4+ ISEN4- IOUT GND EN +12V NTC NETWORK VOLTAGE PROPOTIONAL TO LOAD CURRENT 7 ISL6564A +12V VCC PVCC ISL6612 DRIVER PWM +5V +12V VCC PVCC ISL6612 PWM DRIVER +12V VCC BOOT PVCC ISL6612 DRIVER PWM +12V ...
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... Operating Conditions Supply Voltage, VCC (5V bias mode, Note +5V ±5% Ambient Temperature (ISL6564ACRZ 0°C to +70°C Ambient Temperature (ISL6564AIRZ .-40°C to +85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
Page 9
... When using the internal shunt regulator, VCC is clamped to 6.2V (max). Current must be limited to 25mA or less. 4. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 5. Guaranteed by design. 6. During soft-start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.5V and VDAC + 0.2V. 9 ISL6564A TEST CONDITIONS R = 100kΩ 10kΩ ...
Page 10
... Connecting the 12V supply to EN through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN is driven above 1.29V, the ISL6564A is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN below 1.16V will clear all fault states and prime the ISL6564A to soft-start when re-enabled ...
Page 11
... DRVEN Driver enable pin. This pin can be used to enable the drivers which have enable pins such as ISL6605 or ISL6608. If ISL6564A is used with Intersil ISL6612 drivers, it’s not necessary to use this pin. IDROOP and IOUT IDROOP and IOUT are the output pins of sensed average channel current which is proportional to load current ...
Page 12
... PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6564A is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is an internally generated clock signal which triggers the falling edge of PWM1. The cycle time of ...
Page 13
... HOLD SAMPLE CURRENT, I SWITCHING PERIOD TIME FIGURE 3. SAMPLE AND HOLD TIMING Current Sensing The ISL6564A supports inductor DCR sensing, MOSFET r sensing, or resistive sensing techniques. The DS(ON) internal circuitry, shown in Figures 4, 5, and 6, represents channel N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on the status of the PWM3 and PWM4 pins, as described in the PWM Operation section ...
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... DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6564A to include the combined tolerances of each of these elements. (EQ. 7) The output of the error amplifier, V sawtooth waveform to generate the PWM signals ...
Page 15
... OUT FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT The ISL6564A incorporates an internal differential remote- sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage ...
Page 16
... DS(ON) 1 0.6875V Output-Voltage Offset Programming 0 0.6750V The ISL6564A allows the designer to accurately adjust the 1 0.6625V offset voltage. When a resistor, R OFS to VCC, the voltage across it is regulated to 2.0V. This 0 0.6500V causes a proportional current (I 1 0.6375V R is connected to ground, the voltage across it is ...
Page 17
... DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. The ISL6564A checks the VID inputs at the three edges of 16MHz clock. If the VID code is found to have changed, the controller waits half of a complete cycle before executing a 12.5mV change. If during the half-cycle wait period, the difference between DAC level and the new VID code changes sign, no change is made ...
Page 18
... To enable the controller, VCC must be greater than the POR threshold; the voltage on EN must be greater than 1.29V; For ISL6564A, ENLL must be logic high; and VID cannot be equal to 111111. When each of these conditions is true, the controller immediately begins the soft-start sequence. ...
Page 19
... MOSFETs. If the overvoltage condition 19 ISL6564A reoccurs, the ISL6564A will again command the lower MOSFETs to turn on. The ISL6564A will continue to protect PGOOD the load in this fashion as long as the overvoltage condition recurs. - 110µA ...
Page 20
... FIGURE 15. DRVEN DURING OVERCURRENT OPERATION EN, 5V/DIV FIGURE 16. DRVEN DURING OVERCURRENT OPERATION There’s no need to use DRVEN when ISL6564A is used to work with Intersil’s drivers such as ISL6612 and ISL6605. Current Sense Output The ISL6564A has 2 current sense output pins IDROOP and IOUT. They are identical. In typical application, IDROOP pin is connected to FB pin for the application where load line is required ...
Page 21
... When selecting the equivalent resistor network components values important to ensure the voltage at IOUT pin not exceed 2V. When ISL6564A is operated at single phase mode (both PWM3 and PWM4 connected to VCC and PWM2 unconnected). The output current at IOUT and IDROOP is half of the sensed phase current. ...
Page 22
... RISEN for the affected phases (see the section entitled Channel-Current Balance). Choose R in proportion to the desired ISEN,2 22 ISL6564A decrease in temperature rise in order to cause proportionally and the less current to flow in the hotter phase UP,1 ...
Page 23
... In Equation 24 the per-channel filter inductance divided by the number of active channels the sum total of all output capacitors; ESR is the equivalent-series resistance of 23 ISL6564A FIGURE 19. COMPENSATION CIRCUIT FOR ISL6564A BASED the bulk output-filter capacitance; and V peak sawtooth signal amplitude as described in Figure 7 and . The target Electrical Specifications. ...
Page 24
... The capacitors selected must have sufficiently low ESL and ESR so that the total output- 24 ISL6564A voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount: di Δ ...
Page 25
... Input Supply Voltage Selection The VCC input of the ISL6564A can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300Ω resistor is suggested for limiting the current into the VCC pin to a worst-case maximum of approximately 25mA ...
Page 26
... The while keeping them in close proximity to the microprocessor O socket. The ISL6564A can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors, R feedback resistor, and compensation components ...
Page 27
... Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 27 ISL6564A 4X 4.5 36X 0. 40X ± BOTTOM VIEW ± SIDE VIEW ( 36X ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 28 ISL6564A FN6285.1 March 20, 2007 ...