ISL6569 Intersil Corporation, ISL6569 Datasheet
ISL6569
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ISL6569 Summary of contents
Page 1
... Data Sheet Multi-Phase PWM Controller The ISL6569 provides core-voltage regulation by driving two interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output ripple currents. The reduction in ripple results in lower component cost, reduced dissipation, and a smaller implementation area ...
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... EN 23 FS/DIS 22 PGOOD 21 ISEN1 VID2 20 PWM1 VID1 19 PWM2 18 GND VID0 17 ISEN2 NC 16 VCC 15 GND OFS 14 RGND COMP 13 VSEN FB NC ISL6569CR (32 LD QFN 5X5) TOP VIEW ISEN1 22 PWM1 ...
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... Block Diagram VID4 VID3 DYNAMIC VID2 VID DAC VID1 VID0 e/a FB COMP OFS x0.1 100µA VDIFF VSEN diff RGND AVERAGE IDROOP 3 ISL6569 PGOOD VCC EN 6V POR AND SOFT START 2.2V 90µ 1/2 + GND FS 1.23V OSCILLAT0R AND SAWTOOTH I1 CURRENT SENSE I2 PWM1 PWM2 OVP ISEN1 ...
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... VCC VDIFF PWM1 FB IOUT ISEN1 COMP ISL6569 OFS FS/DIS VID4 VID3 VID2 VID1 PWM2 VID0 PGOOD ISEN2 +12V EN GND 4 ISL6569 +12V PVCC BOOT UGATE VCC PHASE DRIVER HIP6601B LGATE PWM GND +12V PVCC BOOT UGATE VCC R T PHASE DRIVER HIP6601B LGATE ...
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... OFS Current Offset Accuracy OSCILLATOR Accuracy Adjustment Range Disable Voltage Sawtooth Amplitude Max Duty Cycle 5 ISL6569 Thermal Information Thermal Resistance + 0.3V SOIC Package (Note QFN Package (Note 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s .300 ...
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... RGND COMP VSEN Unless otherwise specified. (Continued) MIN TYP - 7.1 3.6 4.5 3.0 7.0 1.6 3 320 350 2.08 2.13 2.2 3.28 ISL6569CR 32 LEAD 5X5 (QFN) TOP VIEW MAX UNITS - dB - MHz 11 V/µ 9 kΩ ...
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... The ISL6569 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagram in Figure 1 provides a top level view of multi-phase power conversion using the ISL6569 controller. ...
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... VDIFF + VSEN RGND FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF A ISL6569 CONVERTER Interleaving The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with the other channel 2-phase converter, channel-2 switches half a cycle after channel- result, the converter has a ripple frequency twice that of either phase ...
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... PWM signal low. SAMPLED CURRENT SEN = I ------------------------- - L1 R ISEN SAMPLE & HOLD - + ISL6569 INTERNAL CIRCUIT FIGURE 4. CHANNEL 1 INTERNAL AND EXTERNAL CURRENT-SENSING CIRCUITRY V IN CHANNEL UPPER MOSFET ISEN ISEN1 - ...
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... During the forced off time following a PWM transition low, the controller senses channel load current by sampling the voltage across the lower MOSFET r DS(ON) referenced amplifier, internal to the ISL6569, connects to the PHASE node through a resistor, R ISEN R is equivalent to the voltage drop across the r ISEN of the lower MOSFET while it is conducting ...
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... The DAC-selected reference voltage is connected to the non-inverting input of the error amplifier. The ISL6569 features a second non-inverting input to the error amplifier which allows the user to directly offset the DAC reference voltage in the positive direction only. The offset voltage is created by an internal current source which ...
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... Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption. The ISL6569 checks the five VID inputs at the beginning of each channel-1 switching cycle. If the VID code has changed, the controller waits one complete switching cycle to validate the new code ...
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... Enable and Disable The PWM outputs are held in a high-impedance state to assure the drivers remain off while in shutdown mode. Four separate input conditions must be met before the ISL6569 is released from shutdown mode. First, the bias voltage applied at VCC must reach the internal power-on reset (POR) circuit rising threshold ...
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... UV threshold. Over-Voltage Protection When the output of the differential amplifier (VDIFF) reaches 2.2V, PGOOD immediately goes low indicating a fault. Two protective actions are taken by the ISL6569 to protect the microprocessor load. UV POR + ...
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... MOSFET or SCR will not overheat before the fuse blows. Once an over-voltage condition is detected, normal PWM operation ceases and PGOOD remains low until the ISL6569 is reset. Cycling the voltage on EN below 1.23V or the bias to VCC below the POR-falling threshold will reset the controller. ...
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... Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 15, 16 ISL6569 the required time for this commutation is t approximated associated power loss ...
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... Capacitors are characterized according to MAX their capacitance, ESR, and ESL (equivalent series inductance). 17 ISL6569 At the beginning of the load transient, the output capacitors ISEN in proportion to the supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL ...
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... DROOP - VDIFF FIGURE 13. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6569 CIRCUIT The feedback resistor has already been chosen as FB outlined in Load-Line Regulation Resistor. Select a target bandwidth for the compensated system, f bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per- channel switching frequency ...
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... V 0 the peak-to-peak sawtooth signal amplitude as described in Figure 5 and Electrical Specifications. Input Supply Voltage Selection The VCC input of the ISL6569 can be connected to either a +5V supply directly or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains , but it can be higher 0 the voltage on the VCC pin when a +12V supply is used ...
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... The ISL6569 can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 21 ISL6569 M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 ISL6569 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...