ISL88015 Intersil Corporation, ISL88015 Datasheet - Page 8

• Manufacturer Part Number: ISL88015
• Description: (ISL88011 - ISL88015) 5 Ld Voltage Supervisors
• Manufacturer: Intersil Corporation

Power On Reset (POR)
Applying at least 1V to the V
which asserts reset (i.e. RST goes HIGH while RST goes
LOW). The reset signals remain asserted until the voltage at
V
level for time period t
have stabilized.
These reset signals provide several benefits:
• It prevents the system microprocessor from starting to
• It prevents the processor from operating prior to
• It ensures that the monitored device is held out of
• It allows time for an FPGA to download its configuration
Adjusting POR Timeout via C
On the ISL88011 and ISL88014, users can adjust the Power
On Reset timeout delay (t
t
C
30pF capacitor to C
250ms to about 2.5s. NOTE: Care should be taken in PCB
layout and capacitor placement in order to reduce stray
capacitance as much as possible, which lengthens the t
timeout period.
POR
DD
POR
operate with insufficient voltage.
stabilization of the oscillator.
operation until internal registers are properly loaded.
prior to initialization of the circuit.
and/or VMON rise above the minimum voltage sense
of 250ms. To do this, connect a capacitor between
and ground (see Figure 3). For example, connecting a
FIGURE 3. ADJUSTING t
5
4
3
2
1
0
6
0
C
10
POR
POR
20
POR
will increase t
. This ensures that the voltages
POR
30
DD
C
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
) up to many times the normal
8
POR
POR
ISL88011
ISL88014
40
pin activates a POR circuit
(pF)
POR
WITH A CAPACITOR
50
POR
Pin
60
from a typical
70
80
POR
Manual Reset
The manual reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active-low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for 1
while the push-button is closed. After MR is released, the
reset outputs remain asserted for t
released.
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t
otherwise the reset signal is asserted (see Figure 5).
Internally, the 1.6s timer is cleared by either a reset or by
toggling the WDI input.
Besides the 1.6s default timeout during normal operation,
these devices also have a longer 51s timeout for startup.
During this time, a reset cannot be asserted due to the WDI
not being toggled. The longer delay at power-on allows an
operating system to boot, an FPGA to initialize, or the
system software to initialize without the burden of dealing
with the Watchdog.
Symbol Table
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
WAVEFORM
ISL88014
ISL88015
ISL88011
ISL88012
ISL88013
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
POR
V
WDT
DD
(200ms) and then
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
R
RST/MR
pu
PB
(1.6s nominal),
December 14, 2006
µ
s or longer
FN8093.1